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Since the processors have more than one level f memory, how is the 2nd level of Cache accessed.

i.e.,

  1. Access both the first level of Cache and 2nd level are Cache are accessed at the same time. If it is a hit in 1st level then it may stop searching in the 2nd level. Disadvantage is higher power dissipation

  2. Second level of cache is accessed only after the miss of first level. So the time of getting the data is more and the processor performance may drastically decrease if the first level of cache is a bit larger

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Choice #2 is correct.

Usually, the L2 cache is both larger and slower than the L1 cache, so it would be impractical to start an L2 cache access every time you start an L1 access.

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    \$\begingroup\$ It might be worth mentioning that for floating point accesses Itanium 2 skipped L1 (L1 was also writethrough). FP use is typically less latency sensitive--never a pointer, rarely a branch determiner, and often high ILP code--and more capacity constrained. L2s are also usually physically indexed and the translation might not be available much sooner than an L1 hit/miss is determined. Since L2 tag access can be pipelined, access time is not a primary barrier; energy use is more important (wasted for 90+% of accesses--L1 hits). (L2 accesses are usually phased: hit detect, then data access.) \$\endgroup\$
    – user15426
    Feb 2, 2014 at 21:54

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