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I am learning the Verilog language. Can someone explain the questions I ask in square brackets [] :

module d_ff(q,d,clk,reset);
     output q;
     input d,clk,reset;
     reg q;
     always @(posedge reset or negedge clk)  [what is this always @()]
     if (reset)
         q<= 1'b0; [what is 1'b0]
     else
         q<=d;
endmodule

For viewing output what is my next step? Does it mean I have to write a stimulus block after this code? What is the meaning of a stimulus block?

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3 Answers 3

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1'b0 is Verilog syntax for a constant value that is a one bit number expressed in binary format with a value of zero.

A bit value of one would be expressed as 1'b1.

Similarly a four bit value in binary that is equivalent magnitude to a decimal value of 11 could be written as 4'b1011.

You could also express this same value in a hexadecimal notation as 4'hB.

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  • \$\begingroup\$ thank you i got meaning of 1'b0... in this case if condition true then q assign 0 value \$\endgroup\$
    – SW.
    Feb 3, 2014 at 8:07
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    //Module definition
        module d_ff(q,d,clk,reset);  

    //Argument Classification: You have to tell the compiler which signals are inputs 
    //and which ones are outputs.

                 output q;
                 input d,clk,reset;
                 reg q;                  

    //Sensitivity list: this is lists all signals that the block will be sensitive to.
   //In the example below the block will run when ever there is a positive edge on the 
   //reset signal or when there is a negative edge on the clock.

                 always @(posedge reset or negedge clk) 

//This is the block of code you want to run when a signal in the sensitivity list is 
//triggered

                 if (reset)
                     q<= 1'b0; 
                 else
                     q<=d;

//End the "d_ff module
            endmodule

To test if this code block works you will need a stimulus block (sometimes called a test-bench).The aim of this block will be to give the module inputs so that you can view the outputs and check to see if the block operates properly.

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  • \$\begingroup\$ thanks killakem..... i know the meaning of always@ now ..... but this propgram run without stimulus block i got the output of D flip flop using this code..... i still do not get the proper purpose and meaning of stimulus block \$\endgroup\$
    – SW.
    Feb 4, 2014 at 5:50
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Anything under always happens sequentially, as in the code works line by line processing rather than by parallel where verilog creates all the wires in parallel, that's why I can put wires in code almost where I want and they will still come out on my diagram where I need them as long as I assign them correctly.

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