Xilinx FPGA Input data timing constraint

Question

I'm using Xilinx Spartan 6 Automotive FPGA. My FPGA design has a SPI interface to a external peripheral.

From FPGA to the peripheral, I have these SPI related signals:

1. spi clk
2. spi data (mosi) - the data is presented on the falling edge of the spi clk

From the peripheral to FPGA:

1. spi data (miso) - the data is presented on the rising edge using the spi clk received from FPGA

FPGA samples the MISO SPI data using the SPI CLK falling edge - it's generated internally (via a state machine).

Now, I want to add a timing constraint on the MISO pin to ensure the MISO data reaches the first sync component (a latch clocked by spi clk) without violating the setup and hold time. Which Xilinx timing constraint should I use?

Some options I was looking into are OFFSET IN, FROM/TO...

I perfer OFFSET IN because it relates data to the clock, but I cannot figure how to specify an internal clock (I don't have SPI clk loopback). FROM/TO might work, but it's not relative to the clock.

Answer 1

I do understand, that you have an internal clock SYS_CLK, which you use to drive the state machine generating SPI_CLK.

The flip-flop which generates SPI_CLK should be located in IOB, to ensure deterministic timing between SYS_CLK and SPI_CLK (you can specify the required maximum delay for SPI_CLK, using the OFFSET OUT).

Then you can specify your constraints using OFFSET IN (for MOSI) and OFFSET OUT (for MISO) with respect to SYS_CLK, considering the delay between SYS_CLK and SPI_CLK.