# Question on Timing Analysis

Hi,

This is a setup-hold time problem given in one of the digital designs book I am using. In the figure(sorry for the poor drawing), a circuit schematic is shown and we have to find out the maximum clock frequency and whether any hold time violations occur or not.

The flip flops(shown with a CLK input) have a clock to Q contamination delay of 30ps and a propagation delay of 80 ps. They have a setup time of 50ps and a hold time of 60ps. Each logic gate(rectangular boxes with operation specified) has a propagation delay of 40ps and contamination delay of 25ps.

I am having a hard time understanding and solving this problem. The book has also provided information regarding setup and hold time constrains in terms of propagation and contamination delays such that

Clock period>=clock to Q propagation delay+combinational logic propagation delay+setup time

and

**clock to Q contamination delay+propagation delay>=hold time**


Can anybody help me with explaining these constraints and the problem solution.

Thanks.

• Do you know what each of these delay types mean? If you do, you can just figure out how many you need of each for you worst-case path and sum them together. I have a suspicion that they are defined in the book you are using. – drxzcl Feb 3 '14 at 22:45