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Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have write operation its operating frequency is 132kHz .voltage compatibility in CPLD is 3.3volt and EEPROM Datasheet describes it will operate from 2.7 volt to 5volt.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:13:36 01/29/2014 
// Design Name: 
// Module Name:    i2c_prorocol 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module i2c_protocol(clk,write,sda,scl_clock,scl);

input clk;
input write;
output scl;
output scl_clock;
inout sda;
//---------------------------------------------------------

reg [6:0] dev_addr_write         = 7'b1010000;
reg [7:0] word_address_write    = 8'b00000001;
reg     [7:0] data                       = 8'b01110101; 

//---------------------------------------------------------

wire  scl;
wire  sda;
//wire  wr_rd_in;
//---------------------------------------------------------
reg     wr_rd=0;
reg     temp_reg=0;
reg     scl_out=1'b0;
reg     scl_out_ss=1'b0;
reg     sda1=1'b0; 

reg     [8:0] state=0;
reg     [10:0] count=0;

reg     scl_clock=1'b0;
reg     slave_ack=1'bz;

//--------------------------------------------------------
//assign wr_rd_in =(wr_rd==1)?1'b0:1'bz;

//---------------------------------------------------------------------------------
always @ (posedge clk)   
begin  

    count <= count+1;
    if (count <=49)
      scl_clock<=0;

    if (count>=50)
      scl_clock<=1;

    if (count>=100)
     count<=0;    

end 

always@(posedge scl_clock )
begin   
     if(write==0)
         temp_reg<=1;   

      if(temp_reg==1)
      if(write==1)
      begin
             temp_reg<=0;
             wr_rd<=1;      
      end   

              if(wr_rd==1)
                        state<=state+1;                 

         case(state)

            7'd0:begin scl_out_ss<=1;sda1<=1;end    
            7'd1: sda1<=0;  
            7'd2: scl_out_ss<=0;

            7'd3: sda1<=dev_addr_write[6];
            7'd4: sda1<=dev_addr_write[5];          
            7'd5: sda1<=dev_addr_write[4];
            7'd6: sda1<=dev_addr_write[3];      
            7'd7: sda1<=dev_addr_write[2];  
            7'd8: sda1<=dev_addr_write[1];
            7'd9: sda1<=dev_addr_write[0];
            7'd10: sda1<=0;
            7'd11: sda1<=slave_ack; 


            7'd12: sda1<=word_address_write[7];
            7'd13: sda1<=word_address_write[6];
            7'd14: sda1<=word_address_write[5];         
            7'd15: sda1<=word_address_write[4];
            7'd16: sda1<=word_address_write[3];
            7'd17: sda1<=word_address_write[2];
            7'd18: sda1<=word_address_write[1];
            7'd19: sda1<=word_address_write[0];
            7'd20: sda1<=slave_ack; 


            7'd21: sda1<=data[7];
            7'd22: sda1<=data[6];
            7'd23: sda1<=data[5];           
            7'd24: sda1<=data[4];
            7'd25: sda1<=data[3];
            7'd26: sda1<=data[2]; 
            7'd27: sda1<=data[1]; 
            7'd28: sda1<=data[0];
            7'd29: sda1<=slave_ack; 

            7'd30:begin sda1<=0;scl_out_ss<=1;end
            7'd31:sda1<=1;
            7'd32:begin state<=0;wr_rd<=0;end
            endcase


end 
assign scl=(state>=4 & (state<=29))? scl_clock:scl_out_ss; 
assign sda=sda1; 

endmodule
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  • 2
    \$\begingroup\$ Are you trying to implement I2C protocol in CPLD to read from an EEPROM? If yes, please have a look at XAPP333 from Xilinx. I have tried this and it works well. \$\endgroup\$
    – Avin
    Feb 4, 2014 at 12:29
  • \$\begingroup\$ Mr Avin can u pls upload that simulation waveform .i am trying to finish this job for past one month but i could not receive bit from EEPROM . \$\endgroup\$ Feb 7, 2014 at 4:51
  • \$\begingroup\$ I don't have the simulation waveforms with me right now. But I remember that the testbench for the code was available with the setup. I had validated the code on one of the boards and it worked well. \$\endgroup\$
    – Avin
    Feb 7, 2014 at 8:16

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