I've read that flash memories can "only" be reprogrammed 100000 to 1000000 times, until the memory storage "deteriorates"

Why exactly does this happen with flash and not other memory types, and what does "deteriorate" refer to, internally?

EDIT: Since it's not only flash that this happens, I'd like to generalize a bit and inquire about the memories that have this problem. Also, does the wearing out between these memory types occur due to the same phenomenon?

  • \$\begingroup\$ The premise is wrong. EEPROM and FRAM (ferroelectric) non-volatile memories also have wear-out mechanisms. \$\endgroup\$ Commented Feb 4, 2014 at 15:34
  • \$\begingroup\$ See also catb.org/~esr/jargon/html/B/bit-rot.html \$\endgroup\$
    – John U
    Commented Feb 4, 2014 at 17:29
  • \$\begingroup\$ @SpehroPefhany Flash and EEPROM are basically identical nowadays, the only difference being Flash is wired in blocks rather than bytes. \$\endgroup\$
    – Nick T
    Commented Feb 4, 2014 at 23:49
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    \$\begingroup\$ As I understand it, NOR flash is not programmed with Fowler-Nordheim tunneling (as are EEPROMs), rather with hot carrier injection like a UV-EPROM. The use of HCI is relevant to this question because it causes faster damage to the cells. NAND flash is more like EEPROM, because Fowler-Nordheim tunneling is used for programming. Not sure what the current market share of each technology is, but I think NAND is on a fairly rapid upward trajectory. \$\endgroup\$ Commented Feb 5, 2014 at 0:06

1 Answer 1


I can't speak about FRAM (ferroelectric memory), but any technology that uses floating gates to store charge — any form of EPROM, including EEPROM and Flash — relies on electrons "tunneling" through a very thin insulating silicon oxide barrier to change the amount of charge on the gate.

The problem is that the oxide barrier is not perfect — since it is "grown" on top of the silicon die, it contains a certain number of defects in the form of crystal grain boundaries. These boundaries tend to "trap" the tunneling electrons more or less permanently, and the field from these trapped electrons interferes with the tunneling current. Eventually, enough charge is trapped to make the cell unwritable.

The trapping mechanism is very slow, but it is enough to give the devices a finite number of write cycles. Obviously, the number quoted by the manufacturer is a statistical average (padded with a safety margin) measured over many devices.

  • \$\begingroup\$ I've seen flash endurance numbers as low as 100 erase-write cycles (min 100, typical only 1000). \$\endgroup\$ Commented Feb 4, 2014 at 16:20
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    \$\begingroup\$ @SpehroPefhany: That's typical for 20 nm TLC (8 levels/cell, 3 bits). At those scales, even a few electrons can cause a shift of one level. MLC (2 bits, 4 levels) has double the level spacing, but the effect is not linear and MLC has far more than double the write endurance. \$\endgroup\$
    – MSalters
    Commented Feb 4, 2014 at 22:05
  • \$\begingroup\$ An interesting (though perhaps not viable) way of overcoming this was presented in this article arstechnica.com/science/2012/11/… over a year ago. Also, contains a diagram of what happens to flash memory over time. \$\endgroup\$
    – qw3n
    Commented Feb 4, 2014 at 22:23
  • \$\begingroup\$ @MSalters This was Microchip.. I think from their Gresham OR fab. PIC18F97J60. I don't know levels or nm (they don't seem to discuss that kind of detail), but I doubt it's anywhere close to what the memory guys are achieving. \$\endgroup\$ Commented Feb 4, 2014 at 22:35

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