I need to run four PCBs with a very accurately synchronised clock.

The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final resolution of about 15ps! I will be measuring the difference in event time between the four boards.

  • I will be using a 1.5ppm source clock, which is enough stability.
  • Any difference in cable length can be calibrated out.
  • What I can't cope with is any change in clock skew over time between boards, because I can't for calibrate this.

I can think of two ways to transmit the clock to the four PCBs.

Clock distributed to four PCBs

  1. Use a clock buffer to drive the clock into four coaxial cables. This will surely rule out any change in clock skew over time, but perhaps the clock won't have enough drive to inject into 4x 50R lines. An ultra-low skew quad clock buffer chip, like the NB3N551 lists an output impedance of 20R, which is greater than the 12.5R of the cables.
  2. Use four clock buffers, which will have enough drive, but can the buffer-buffer skew change with time? The NB3N551 lists an output-output skew of typically 50ps and max 160ps. But it doesn't explicitly state the stability of that skew.

Is there anything which rules out one of these two solutions? Which is the best approach for achieving ultra low skew drift?

If I used method 2, would it be better to use series termination instead?

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    \$\begingroup\$ 15ps represents about 3% of the typical \$T_R \$and \$T_F\$, you'll need very clean power supplies and to minimize effect of reflections from impedance mismatch. I don't think your drivers (especially when located on one monolithic chip) will be the biggest source of trouble. \$\endgroup\$ – Spehro Pefhany Feb 5 '14 at 16:08
  • \$\begingroup\$ Doesn't "RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)" tell you what you want to know about stability? \$\endgroup\$ – Dave Tweed Feb 5 '14 at 16:50
  • \$\begingroup\$ @DaveTweed - I don't know. I thought that jitter was a high frequency thing, while skew was a low frequency thing. I assume they're measured differently, and that skew drift wouldn't be measured as part of phase jitter. \$\endgroup\$ – Rocketmagnet Feb 5 '14 at 16:59
  • \$\begingroup\$ @DaveTweed The 12kHz high-pass would remove almost all thermal drift component. \$\endgroup\$ – Spehro Pefhany Feb 5 '14 at 18:16

Rather than connect 4 buffers to a single input net, or drive multiple lines with a single buffer, you can use a fanout buffer IC.

For example, MC100EP14 is a 1:5 fanout buffer with 35 ps maximum skew between the outputs of an individual chip. The drift of this skew is not explicitly specified, but you can guess at it from the other specs. Typical propagation delay increases by 5 ps when the operating temperature changes from 25 to 85 C. If you imagine that the individual output buffers on the chip vary by +/- 5 C relative to each other, you can estimate that the skew will drift by 0.5 ps or less due to thermal effects, which are likely to be the dominant issue.


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