I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I believe the Virtex-5 provides an option for a BRAM and while I understand that the depth is nowhere close to what the SRAM provides, I'd like to make use of the BRAM option in the Virtex-5 as a buffer to hold the samples temporarily until they are acquired by the PC. How difficult would this be to implement ?
Good news. This is a really common application for ADC interfaces. It's actually very easy to set up the block RAM in Xilinx devices.
You will want to run the "Block Memory Generator" Coregen by Xilinx, which will generate basically a black-box VHDL module that you can instantiate in your top level VHDL module. In the coregen, you can customize your block RAM so that it "looks" just like your existing external SRAM. The only difference will be that you will be connecting signals in your top-level module to the new black-box module that you've instantiated instead of to your external pins.
I'm not sure that you can get a data width of 256 (did you really mean 8?), but I think that you could get a depth of 128K on most Virtex-5 devices. The datasheet showing the Virtex-5 resources table (how much BRAM is available) is available here.
The datasheet that explains Block Memory Generator is here. It can explain the settings, etc.
To launch the block memory generator in ISE 14, right click in the project heirarchy and select "new source". Then select source type as "IP (Core...". Then select Block Memory Generator as the IP type as shown below.
Once the "Block Memory Generator" opens, select whichever options you want, then click configure. It will add the black-box core to your project. You will have to instantiate it in your top level module. You can usually see the "instantiation template" by clicking the core in the project heirarchy and selecting the "View HDL Instantiation Template" in the processes window.
Block RAMs are very easy to get the tools to produce from HDL code - no need to mess with Coregen.
The advantages of doing it without coregen are:
- No extra tools in the flow
- you can use constants and generics (or their Verilog equivalents) from the rest of your design to configure the memory depth and width
- coregen can add several minutes onto a compilation run when you've changed something, whereas a quick tweak to an HDL file doesn't change the compilation time by a noticeable amount in my experience. I have no idea what Coregen is doing all that time!
Check your synthesiser manual for how to write code that will infer block ram, and there are some examples in the answers to this question