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I am doing a design using System Generator, and I have some doubts if my design could be performed in a Virtex 4 FPGA.

Does anyone know what can I do to check this?

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  • \$\begingroup\$ Can anyone create a tag called 'howto'? \$\endgroup\$ – Peterstone Feb 10 '11 at 9:03
  • \$\begingroup\$ You have some "Dudes"? ..... What? Do you mean "doubts"? \$\endgroup\$ – Connor Wolf Feb 10 '11 at 11:03
  • \$\begingroup\$ @Fake Name - Fixed. \$\endgroup\$ – Kevin Vermeer Feb 10 '11 at 14:28
  • \$\begingroup\$ Sorry, that what I wanted to say "doubts". Thank you to fixed. \$\endgroup\$ – Peterstone Feb 10 '11 at 18:40
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Go on Xilinx's DSP course - that'll give you a really good feel for how much resource various dsp-type operations take up, and then you'll be able to estimate in your head.

Otherwise, you'll just have to build it and see. To get a quick idea, generate the NGC from the sysgen block and use FPGAOptim to show you which blocks are using how much of which resource. It'll not be the final final answer, but within a few percent of the LUT count. (Full disclosure - I wrote FPGAOptim at work)

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  • \$\begingroup\$ FGPAOptim is free? \$\endgroup\$ – Peterstone Feb 11 '11 at 6:25
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    \$\begingroup\$ Yes, FPGAOptim is free \$\endgroup\$ – Martin Thompson Feb 11 '11 at 8:25
  • \$\begingroup\$ I like this approach. If I went to an architect to design a house on a budget, I wouldn't accept a cost estimate of "build it and see". However, I wouldn't expect the estimate to be perfect, either. As its being built the plan gets optimized to stay within budget. But avoid premature optimization. Build up your design in sections and only optimize if profiling shows a section is taking significantly more resources than you estimated. If one section goes a little over budget, on the other hand, it might balance with a section that's under budget. \$\endgroup\$ – Eryk Sun Feb 11 '11 at 23:48
  • \$\begingroup\$ @eryksun: except the difference is it costs a fortune to build it and see with a house... Not so with software. Take advantage of that \$\endgroup\$ – Martin Thompson Feb 14 '11 at 18:13
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Well, there was always only 1 universal way to find out: run synthesis of your design for target FPGA and see if it feets in and meet timing constraints.

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