# Difference between setting up clocks on Verilog

These two statements are used quite often, to set up clocks in test benches:

initial
begin
clock = 1'b0;
forever #5 clock = ~clock;
end


always
begin
clock = 1'b0;
#5 clock = 1'b1;
#5;
end


Is there any difference between the two or are they 100% equal and interchangeable?

Your examples are basically the same. However, I only use the first example, with a define for the cycle count. Here's a snippet from my code:

define CYCLE 100 // in nanoseconds
....

// create a clock depending on the CYCLE setting
initial begin
clk = 1'b0;
// every half-CYCLE invert
forever #(CYCLE/2) clk = ~clk;
end


I prefer to use an initial block for my testbench clock because initial blocks are never synthesized. So putting it inside an initial block makes is quite clear that this code is only for simulation.

I tend to use another form, which is somewhat shorter

reg clk = 0;
always #3.2 clk = ~clk; // 156.25Mhz
`

I have no idea if either are cheaper at runtime for the simulator.

• I don't think it matters. My only reason for preferring an initial block is that it becomes immediately clear to anyone looking at the code that the block is strictly intended for simulation, because initial blocks are never synthesized. In your example, although I see #3.2 and know that is not synthesized, I still have to dig through the code to find out if clk is real or for simulation only. In this simple case it might be immediately clear, but other cases can be more complex. So best practice might be to use an initial block to be the clearest. Cheers! – Brian Onn Feb 14 '14 at 21:00