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Using JK or T flip-flops, it's easy to create a synchronous N-bit counter by cascading them as depicted here:

a 4-bit counter with T flops and no feedback loops

The above circuit has no feedback loops in it. I have run into a situation where I would prefer to use D flops, but I also want to avoid unnecessary loops because of wiring congestion. My intuition says doing both (using D flops and avoiding feedback loops) is impossible, but I can't really put my finger on why. Both types of flip-flops save 1 bit of state, right? Sticking a feedback loop in on top of the D flop feels like adding another piece of state, but the system as a whole doesn't store any extra data.

Am I thinking about loops incorrectly? What's different about the D flip-flop that makes it not work here? Last and most important, is it actually impossible to make a counter using only D flops and no feedback loops, or am I just too close to the problem to see it?

Edit to clarify my question: Both D and T flip-flops have some kind of internal feedback loop; I understand that. Both D and T flip-flops store one bit of information. What is different about the T flip-flop that allows it to be used in a counter without adding more feedback loops? Or, alternatively, what about the D flip flop makes it inadequate for this purpose when used alone?

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  • 2
    \$\begingroup\$ It's not synchronous. \$\endgroup\$ – Andy aka Feb 11 '14 at 22:07
  • \$\begingroup\$ Most likely, your T flip-flops are implemented as DFF's with feedback, as shown in Andy's answer. \$\endgroup\$ – The Photon Feb 11 '14 at 22:33
  • \$\begingroup\$ Thanks Andy, I was in a hurry when I posted and didn't realize my mistake. Found another circuit that demonstrates the circuit I'm talking about. \$\endgroup\$ – trentcl Feb 12 '14 at 13:34
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To make a T flip-flop, you take a D-flip flop and add feedback from the output to determine the next state.

The immage bellow shows the most basic operating logic of a T flip-flop. If you removed the feed back from Q and Q' you get a D flip-flop (And I know, you also have to invert the bit input on the lower and gate. Lets keep it simple, ok?)

T Flip-Flop

So when you go to use a D flip-flop in a counter circuit instead of a T flip-flop, you have to manually add in the feedback that is now missing.

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  • \$\begingroup\$ Ok, this is a partial answer, but looking at it from a systems perspective: a D FF has a feedback loop in it already. Why do I need two feedback loops, one inside the FF and one external to it, when I need only one bit of state? \$\endgroup\$ – trentcl Feb 12 '14 at 17:04
  • \$\begingroup\$ Actually, the most basic D FF does not have a feedback loop since the output state on the next clock cycle does not depend on the current output state. Like I said above, if you take the T Flip-flop pictured and remove the feedback from the output, you will get a D Flip-flop. \$\endgroup\$ – Gaddiel Feb 12 '14 at 17:39
  • \$\begingroup\$ Any FF or latch needs a feedback loop in order to have state at all; I refer you to @OlinLathrop's answer. But I think I see why that doesn't apply in the way I thought it ought to. \$\endgroup\$ – trentcl Feb 12 '14 at 18:40
  • \$\begingroup\$ I'm calling this the accepted answer because, while it doesn't exactly address my confusion, I'm seeing now that there's a difference between what the two (kinda 3) feedback loops do in that diagram. Thanks \$\endgroup\$ – trentcl Feb 13 '14 at 17:01
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The D type flip flop needs feedback from its inverted Q output to divide frequency by two. That's the short and long story: -

enter image description here

The way a D flip flop works is simple. Positive clock edges latch the state of the D input at the time the edge rises. Therefore by the time the QBAR output has changed state (some few nano seconds later), its previous state has already been latched so there are no glitches.

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  • \$\begingroup\$ @trentcl: The D FF with feedback as Andy shows IS your T FF (as the Photon remarks). Hence adding that feedback wire is simply wiring your D FF (what you have) to behave as T FF (what you want). Those wires are present in your diagram too, but they are inside your T FF blocks. \$\endgroup\$ – Wouter van Ooijen Feb 12 '14 at 8:18
  • \$\begingroup\$ (Changed the circuit in the original, in case you want to adjust your answer.) So adding a loop doesn't affect the... "statefulness" of the circuit? It just seems odd to me that a T flop can do by itself what a D flop can't, being that they both save one bit of state. But I guess it makes sense that the feedback loop is implicit in the T flop. \$\endgroup\$ – trentcl Feb 12 '14 at 13:36
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If one is willing to make certain assumptions about propagation delays, and can generate a suitable-length pulse from each rising clock edge, a T flip flop doesn't need anything more than an XOR gate which feeds back to itself.

schematic

simulate this circuit – Schematic created using CircuitLab

The circuit above uses RC circuits to add propagation delay to the XOR gate; the comparator at the lower left generates various widths of clock pulses. If a clock pulse is too short, it won't make the output switch; if it's too long, it will switch more than once (as shown, pulses range from being too narrow to switch at all, to being wide enough to switch three times). Note that the default gates and logic buffers in this simulator have Schmidt trigger inputs (which implies the existence of internal feedback) but the analog comparators don't, so the circuit as drawn has no feedback path other than the single wire across the top.

In practice, trying to condition clock pulses to be just the right width is impractical, so flip flops add additional internal feedback structures. Such structures require more circuitry, but having a larger amount of robust circuitry is better than having a smaller amount of circuitry which requires precise tweaking to make it work.

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  • \$\begingroup\$ Interesting. As a matter of fact, in the technology I'm using (superconducting logic), it's possible to make a similar circuit without using RC circuits to finagle the pulse width. However, the tradeoffs are weird (DFFs are cheaper than XORs, for example). Thanks! \$\endgroup\$ – trentcl Feb 20 '15 at 13:29
  • \$\begingroup\$ @trentcl: In NMOS technology, I would think an XOR whose inputs were used for no other purpose could be realized with two active transistors and a passive pullup; I don't know if any manufactured chips used such a circuit. I'll readily admit that because there are different realizations of XOR with different performance characteristics, using one in a schematic is perhaps a bit of a "cheat". Still, the RC circuits in the above schematic were not intended to be indicative of "deliberate" RC circuits so much as to parasitic RC behaviors. Since you mention superconductors, I'm curious... \$\endgroup\$ – supercat Feb 20 '15 at 16:40
  • \$\begingroup\$ ...what are the performance characteristics of superconducting gates? In this simulator, gates act as delay lines, which is IMHO highly unrealistic for any "normal" kind of logic; if I were designing a simulator, I'd define Tp(min) and Tp(max) and say that the output of a gate will go to mid-rail Tp(min) after any change to the input which could affect the output, and only become valid Tp(max) after the inputs have become valid; under such a simulation, some circuits which would in real life behave sensibly could get stuck with everything at mid-rail, but circuits that work under simulation... \$\endgroup\$ – supercat Feb 20 '15 at 16:44
  • \$\begingroup\$ ...with reasonable parameters defined on the underlying components would work in reality with any combination of of real-world behaviors between Tp(min) and Tp(max)--a situation which is not verifiable when simulators use a fixed propagation time. Do superconductors behave like delay lines, or inertial gates, or something in-between? \$\endgroup\$ – supercat Feb 20 '15 at 16:45
  • \$\begingroup\$ It depends on the specific logic family involved, but in general, you find that gates tend to have a latch or flip-flop "built-in", because their delay always depends on a clock. Notionally, they behave more like delay lines, but in context the clocked nature of the circuit dominates any question about the behavior of the actual gate. Beyond that, it depends on the implementation (RQL, or some RSFQ variant, which are numerous). Does this begin to answer your question? \$\endgroup\$ – trentcl Feb 21 '15 at 10:47
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Every flip-flop inherently has some feedback inside. Consider the very simple case of a R-S flip-flop:

Other types of flip-flops start with this basic one and add stuff around it.

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  • \$\begingroup\$ This is what's confusing me. A D FF has internal feedback. A T FF has internal feedback. Both types of flip-flop store the same amount of information: one bit. Why do I have to add more feedback to make the D flop work as a counter? \$\endgroup\$ – trentcl Feb 12 '14 at 14:26
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A ripple-through counter uses T-flops (toggle flip-flops which may be either JK-flops with J and K held high, or D-flops with /Q connected to D) with no feedback between them. They are useful for dividing by powers of 2, can handle high input frequencies limited only by the first flip-flop, but their output(s) do not change synchronously due to accumulating delays. http://en.wikipedia.org/wiki/Counter_(digital) >**Asynchronous (ripple) counter

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