# Input Protection for an Electronic Load

I'm currently working on a dummy load designed for testing small power supplies less than about 10V. I'd like to provide reverse input protection to prevent the op-amps from being damaged. Because the load has to measure the input voltage (constant power and resistance operation), the voltage drop across the input protection needs to be as small as possible.

I've thought about using a P-channel MOSFET, but that requires that the input voltage be above the MOSFET's Vgs threshold, which would be above the minimum voltage I want this load to be able to test (under ~1V ideally). Also, this would cause large voltage drops and power dissipation when the input voltage is near the MOSFET's Vgs threshold.

Another solution I've seen is a zener with a fuse/PTC. PTCs are too slow to trigger and fuses have to be replaced, so that doesn't seem to be a great solution.

The simplest solution that I can think of is a single diode, but this is also not ideal because of the rather large voltage drop (min. of about .3v with a schottky).

Here is my current circuit:

simulate this circuit – Schematic created using CircuitLab

I appreciate any ideas you all have to offer!

EDIT: I forgot to mention that this IS NOT powered from the power supply under test. It's going to be battery powered so I'm thinking 2 3v coin cells in series regulated to 5v.

Also, I don't think I was clear about what I meant by using a P-Channel MOSFET: https://www.circuitlab.com/circuit/bka32t/p-channel-protection/

• Something went wrong with the circuit attachment. Feb 11, 2014 at 23:12
• That was fast! Should work now. Feb 11, 2014 at 23:12

For reverse-voltage protection, you could consider (conceptually) something like this. Diodes are the inherent body diodes of the N-channel MOSFETs, not discrete components.

Each input could go negative as much as one (body) diode drop so some biasing may be necessary depending on the amplifier/comparator, perhaps a resistor to ground on each input of the comparator and a resistor to +5 to bias the input above ground. Some amplifier/comparators may require only a divider network.

Anyway, if Vx is negative, then the output of U1 is ~0V so Q2 stays off, and Vx can be as high as the breakdown voltage of Q2 without causing damage (assuming R4, R5 are high enough to avoid damage to U1). If Vx is positive more than a few mV, then Q2 turns on fully, adding only milliohms to the circuit.

simulate this circuit – Schematic created using CircuitLab

• I'm building this circuit up and I'm still a bit confused about one thing. What exactly do you mean by "Each input could go negative as much as one (body) diode drop"? Wont the comparator and Q2 automatically turn off and prevent any current flow? Feb 13, 2014 at 1:57
• It should, but if the comparator does something funny (because the input common mode range has been exceeded), it might not. Some parts (eg. LM324) will reverse phase if an input is brought below ground, causing latching. Better to make sure it works under all possible inputs. Feb 13, 2014 at 3:31
• My supply voltage (5V) is potentially less than the input voltage, which will be up to 10V. I can simply divide the input voltage and then bias that, correct? Feb 14, 2014 at 0:17
• Yes, so 3 resistors per input. Feb 14, 2014 at 0:58
• Is this what you had in mind? It seems to work well in CircuitLab. I chose the resistor values to be as high as I thought practical. Should they be changed?circuitlab.com/circuit/7gzsm4/electronic-load Feb 14, 2014 at 1:54

You'll want to put a 10k resistor in the path from the FET source to the -ve input of the op-amp. You don't want that directly connected there, and you're only sensing voltage. However, be careful of the input bias on this op-amp, it will causes a voltage drop across the 10k and add error, so choose a resistor that is low enough to not add significant error to your voltage sense, or a precision opamp with low input bias currents.

You also want to put a 10 ohm up to 100 ohm between the opamp output and the gate of the FET. The op amp doesn't want to drive the capacitive gate and the 10-100ohm there along with the gate capacitance forms a pole that stabilizes the loop. Some people like to add extra capacitance from the gate to GND if the loop still oscillates and they need it even slower.

For reverse voltage protection, perhaps you can use the current sense resistor as it is there, and either a depletion mode FET (if you can work out the Vgs issues) or simply a relay. Note that when the load is connected in reverse the body diode of the MOSFET is forward biased, and the sense resistor and MOSFET is in the current path. This will be high current and you can sense that, and you can also sense it's in reverse by the polarity across the sense resistor.

Furthermore, you cannot power these from the LOAD. you must have independent power for the opamps. You can share a ground, that's all.

For a more advanced design, you can float the output section and power that from a separate supply. Closing the loop from the MOSFET to the op-amp would be via opto-isolators or signal transformers in both directions.

• Thanks for the suggestions about the feedback resistors. I'll make sure to add those. Also, this op-amp is just one I've been using in CircuitLab for simulation. I'm not sure what I'll use in the final design. The depletion mode FET is an interesting idea, but how does that prevent the negative voltage from killing the measurement op-amps? Are high value resistors enough to protect those? Feb 12, 2014 at 0:53
• The easiest way to think about the reverse application of the load PSU is to consider the node at the drain of the FET. If your PSU was 15V, and you put it on in reverse, the ONLY thing your circuit would see is that node at -15V. everything else is the same; GND would not suddenly go up to +15V, but that node will come down. So look at that point, and determine what will happen when that node at the drain of the FET is -15V (or your maximum PSU voltage, if you are testing 48V PSUs that point will be -48V. How can you protect your circuit now. :) Feb 12, 2014 at 1:05
• I'll start you off.. Assuming you power the op amps from their own power rail, and you put -15V at that node, the following is true: OA3 is safe from harm, it only sees -1.5V at it's input and no current. Feb 12, 2014 at 1:22
• OA6 is still safe... it only sees the differential voltage across the R1 sense resistor, just as before, only now the voltage is reversed. The -ve input is more negative than the +ve input, so the output goes to GND. 0V. The FET is ok with this particular situation (gate at 0V). [ note: if you power OA6 with a bipolar supply, you can have it go below GND in this situation.. (the FET may not like that, you'll need a diode to the gate now)... but this negative swing of the output can be your reverse polarity indicator and drive other logic to disconnect the load :) Feb 12, 2014 at 1:31
• So just to clarify, we're talking about using a depletion FET right? As long as the FET is off, OA6 and OA2 should be fine because they are both measuring the drop across the resistor, correct? Feb 12, 2014 at 3:18

If you have op amps in your dummy load then you cant power them from the power supply your testing if it is only providing 1 volt. This has to mean that your dummy load has an external supply and if it has then what is the problem using that to generate sufficient negative voltage to turn your p ch fet on? Maybe I'm missing something here?

• Thanks for the response! I forgot to mention that this IS NOT powered from the power supply under test. It's going to be battery powered so I'm thinking 2 3v coin cells in series regulated to 5v. Based on the input protection circuit I just added in the edit, is it still feasible to create a negative voltage? How would I make that respond to a negative input voltage? Feb 12, 2014 at 0:31