# design data storage using a simple MUX instead of a complicated SR latch

I was studying sequential circuits and I am at the very infant stages of the course. After studying the D flipflop I realized that the purpose was to let the data line change the output if clk=1 or keep the data same if clk=0. The circuit that is generally used is derived out of the SR latch which is a complex circuit using two feedbacks. Why cant I use a simple one feedback MUX circuit with the following boolean function?

Q(n+1)=Qn.C*+D.C

simulate this circuit – Schematic created using CircuitLab

The circuit diagram at the gate level would be as shown above, where D is the data line and C is the Clock. Am I being dumb somewhere??

• No, your circuit is not a flip-flop, at least not how I define that term. A flip-flop is an edge-triggered storage element while a latch is a level-sensitive storage element. Your circuit is a level-sensitive D-latch. The signal you have called C is a latch-enable signal, not a true clock. – Joe Hass Feb 12 '14 at 22:09