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Is it ok to use an "ordinary" via to connect the Exposed Pad of an TQNF package to ground, as shown in the following picture?

I am using eagle. DRC generates an "overlap" error, is it ok to ignore this error?

Can this design cause board assembly issues (I'm planning to do machine assembly)?

enter image description here

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  • \$\begingroup\$ If that isn't a tented via, it should work fine, I believe. If the via is off-center that might cause some issues, but as it stands, it is no different than thermal vias for heat-sinking pads for various parts. \$\endgroup\$ – Anindo Ghosh Feb 12 '14 at 10:06
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    \$\begingroup\$ Note that if you're doing machine assembly, having non-capped/filled vias in the exposed pad can pull solder away from the pad, causing potential contact issues. However, if you're manually soldering the PCB, you can always just flow solder in the back-side of the via to fix the issue. \$\endgroup\$ – Connor Wolf Feb 12 '14 at 10:35
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Vias will not impact the assembly of the PCB provided that their effect is carefully considered in the assembly process.

enter image description here

Many RF ICs and SMD power MOS devices require solid thermal connections to internal planes in order to wick away generated heat and endure a low impedance GND path. Vias are known to wick up solder paste during the reflow process and there are several options to mitigate this. The correct combination of via count, via size and solder paste mask will ensure a very repeatable assembly process.

The screen capture above is of a GPIO expander with 16 non-plugged vias which are tented only on the bottom side. It is a 6 layer board with solid 1oz ground planing on all layers. Paste mask is revealed in grey. Most IC manufacturers will specify the solder paste and via requirements, otherwise it may be extracted from IPC-7351-2004 Generic Requirements for Surface Mount Design and Land patterns. There are also many free and open source land pattern generators online.

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First of all, one via isn't going to move a lot of heat. The reason the chip has a pad on the bottom is for thermal control; the idea is to have a good thermal (not just electrical) connection to a large area of copper (e.g., ground plane).

Secondly, vias-in-pads cause problems with reflow soldering — unless the vias are covered or plugged, they tend to wick solder away from the surface of the board, making the electrical (and thermal) connection unreliable.

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