Questions tagged [8085]

An eight bit microprocessor made by Intel in 1976.

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Chip select for the ROM

An 8 Kbyte ROM with an active low Chip Select input (CS') is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000 H to 2FFFH. The address lines are designed ...
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DAA operation in 8085 microprocessor

Let the content of register A is 98H. Both Auxiliary Carry flag and Carry flag are set i.e. AC=1 & Cy=1. If now I execute DAA once, both nibbles will get added with (0110) and the result is FEH ...
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Why does the conditional CALL instruction in the 8085 microprocessor take 2 machine cycles, when the condition is not satisfied?

When the condition gets checked in the 6th T-state itself and is found to be not satisfying, why does it need the 2nd machine cycle?
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8085 Microprocessor programming kit

When the power of the kit 8085 trading kit is turn on, UP-85 is displayed. How is it possible something is displayed even before entering anything?
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8085 : Storing data in stack

In 8085 whatever address the stack pointer holds, we always start storing bytes from one less than this address . Eg. If SP holds 2008H. We will store 16-bit data at 2007 and 2006H. Why don't we store ...
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8085;Condition CALL Instruction: if condition fails

In call instruction there are 5 machine cycles S,R,R,W,W (S is 6 T-states opcode fetch) and thus 18 T-states In first machine cycle, t1-t4 is utilized for fetching the opcode and decoding it and t5-...
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MOV C, B instruction in 8085 takes 4T cycles so when and how does the data copies from B to C

As specified all over the internet, MOV C, B instruction in 8085 only takes 4T states to execute but the opcode fetch and decode take 4T states, which means the transfer of data from one register to ...
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8085 ;JMP instruction

How exactly is JMP XXXXH; executed ? First the PC(Program counter) will contain the address where this instruction is present. In first machine cycle opcode will be fetched and PC will be incremented ...
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1answer
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8085 ; High impedance state of lower order address/multiplexed data bus during memory read and write machine cycles

The two pictures are of memory read and write machine cycles . Could somebody please explain why in memory read cycle the lower order address / multiplexed data bus is in high impedance state at the ...
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8085 SIM instruction don't care bit

While reading about the SIM in 8085 i came upon the accumulator state at the data pin 5 where when SIM instruction is executed we have to consider pin 5 of the accumulator to be don't care. So I am ...
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8085; Why RET doesn't require a 6 T-states Fetch cycle?

The CALL instruction, requires 5 machine cycles, namely, OPCODE-FETCH, MEMORY READ, MEMORY READ, MEMORY WRITE, MEMORY WRITE. The ...
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8085 μp; Why does Read cycle take 3 T-states and not 2?

In the text I'm following, R.S.Gaonkar it's explained that, During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR), During the falling edge of T2 \$\overline{MEMR}...
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8085 MPU; Stepping through an instruction (Timing diagrams)

Let me write the steps of ADD B, as I've understood it till now. T0: ALE goes high Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
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What is the minimum size of that a segment can take in 8086? [duplicate]

I know that the minimum distance between any 2 segments is be 16 locations (10H) , but some say its 16 bytes , how is that possible if the the locations are of 2 bytes each. It would total to 32 bytes ...
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If we can access (64*4) 256Kb of memory at a time in 8086 and you can move those segments around, what is the use of the remaining memory

If we can access (64*4) 256Kb of memory at a time in 8086 and you can move those segments around, what is the use of the remaining memory? Some say that we can move around the segments but what is the ...
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Design an interfacing circuit/address decoding circuit to interface one 4KB EPROM and two 2KB R/W memory for 8085 microprocessor?

I don't know if this question is a good question to get answers or not but I am trying to honestly explain my situation. I am studying 8085 microprocessor, so I am stumbled upon address decoding ...
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263 views

how to write a 8085 assembly language to sort 5 data bytes in ascending order [closed]

Needed advise on how to program using 8085 simulator. tried many ways but could not get the answer
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How do I produce WE in this diagram?

I have designed a memory system that has 10KB ROM followed by 6KB of RAM. The ROM begins at 0000H. I had to use two 4K x 8bit ROMs and one 2K x 8 bit ROM. I also have to use one 2K x 8bit RAM and a 4K ...
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160 views

Is a multiplexer needed to read from memory

we need to enable a register to write into that register, which is done using a decoder. even if we enable 1 register using decoder, given that RD(bar) is 0, all registers can still produce an output. ...
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Microprocessor 8085 regains control of the bus

a) immediately after HOLD goes Low b) immediately after HOLD goes high c) after half clock cycle has passed once HLDS goes low d) after half clock cycle after HLDA goes high This question was asked ...
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102 views

Building a simple manual Intel 8085 study kit

I am toying with the idea of building an Intel 8085 demonstration/study kit which would consist of an Intel 8085 microprocessor on a PCB, where all input nodes (including the clock X1, X2) would be ...
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Why RST instructions are called one byte call instruction in 8085 [closed]

Why RST instructions are called one byte call instruction in 8085 ?
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Parity flag in 8085 microprocessor

What happens to the parity flag of an Intel 8085 microprocessor when there is no '1' bit in the accumulator? For example, if the following instruction executes, MVI A, 05H MVI B, 05H SUB B the ...
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What is increment/decrement address latch in 8085

Can you please explain about increment/decrement latch in 8085. I am currently studying registers and encountered this in the array of register section. Here are the things i found when i googled and ...
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105 views

IO mapped IO design problem

While going through the solution of the above problem i noticed something like below. Address of port A becomes 11100000. Can't get that. I am confused why it's not 01100000. Thank you!!
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What is the best way to implement spi using 8085? [closed]

I have to make a compass using 8085. I have to take serial data from magnetometer of mpu9250. Should i prefer bit banging to implement spi or make parallel out and parallel in hardware using shift ...
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Why don't we have an instruction called LDAX H in 8085 microprocessor?

Whereas we have instructions such as LDAX B , LDAX D !!!
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Microprocessor 8085

What is the need of enabling 8 bit register in memory using address bus to read data from it?Enabling is required to write data into register and after that to read can't we just provide read signal ...
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8085 Programming Basics

Bcz of CALL, SP will be decremented by 2. Then bcz of POP, SP will get incremented by 2. So, SP will be 27FFH. But, I am confused with HL register part. Please help me with the above problem.
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Why is there no tri-state during T2 state of this machine cycle?

My teacher provided this as part of printed notes where he writes there is no tristate during the T2 state of Memory Write Cycle. I am quite confused about why it is so. After a short search in the ...
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8085 - binary equivalent of MOV and it's corresponding timing diagram

I've got two questions here: #1 The MOV A,B is said to be a one byte instruction, where B = 000 and A = 111, then MOV should be equal to 00, but, The binary representation of the BC Rp is 00. So, I'...
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How to save carry bits in 8085?

Suppose two 16bits numbers are added in 8085, then there is a carry, so, how do I save the carry into a memory location?
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8085 programming the ani instruction

Why is the AC flag set while using the ANI instruction in 8085: MVI A, A3H ANI 97H HLT The sign flag is set which is ...
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In microprocessor 8085, how can I clear/reset all flags(s,z,ac,p,cy) without affecting contents of accumulator? [duplicate]

I only know the code in which accumulator contents are affected. It is not a duplicate as I have asked for a solution which doesn't affect accumulator.
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Why the address of 8085 interrupt are 8 locations apart and not in continuation

If it's for Interrupt Service Routine (ISR) in which microprocessor pushes the content of program Counter(PC) to stack and then loads the Vector address in PC and starts executing the ISR stored in ...
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What exactly is latch?

I've very less knowledge in electronics, I've read that a latch is a simple circuit that stores 1 bit of data (or state). A Latch is a circuit that has two stable states and can be used to store ...
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Overflow results into wrong sign-flag bit set in 8085 microprocessor .

In case of 8085 microprocessor when the MSB bit of accumulator is 1 then sign flag becomes 1 ( simply copy the result's msb) , my question is that : When we add two positive numbers say 44H(01000100) ...
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333 views

HOLD signal in 8085

What happens to an 8085 system if a square wave signal of 1KHz frequency is applied to the HOLD signal of 8085? The frequency of operation is 2MHz. Therefore, if the every 0.5ms, the HOLD pin goes ...
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Pending interrupts in 8085

I've gotten a little confused with what the definition of the pending interrupt is. That is when will this bit be set to 1 and read by using the RIM instruction. My confusion is that: When an ...
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does 8085 CPU have an extra register within ALU?

From the 8085 CPU architecture, when ALU done calculation, the result is clocked back to accumulator A on next clock edge. But accumulator A is directly wired as ALU input, what if the clock edge didn'...
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235 views

Slow clock for 8085

I want to find out if my purchased 8085 works. I'm thinking of: pulling down the data bus and interrupt lines (equivalent to NOPs) using a slow RC clock (1 Hz or so) drive LEDs through BJTs with the ...
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Invalid opcodes

What happens when a microprocessor like the 8085 fetches an invalid opcode, i.e. not part of its instruction set, from memory and attempts to decode and run it? I found, in some forum, that invalid ...
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Building an Intel 8085 trainer

I'd like to build an Intel 8085 trainer for a final year project. The trainer will be used by students and will basically accept machine code entered by students, load these into RAM and run the code. ...
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How to determine no of bytes of an instruction of 8085 microprocessor?

Is there any logical way to understand no of bytes corresponding to an instruction in 8085 microprocessor? e.g: MOV A,M is a one byte instruction, but how, I don't understand. Or do I have to ...
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Does an ALU always do add and sub, but only returns one of the results?

Pretty simple question. Does an ALU internally always do multiple operations like add, sub, div, mul, ... and you simply have to specify which result you want to return? I was told that it does that, ...
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Address Decoding in 8085

RAM (8KB, requires 13 bits A0-A12) Start: 0110 0000 0101 0000 (6050h) End: 1000 0000 0100 1111 (804Fh) ROM1 (8KB, requires 13 bits A0-A12) Start: 1000 0000 0101 0000 (8050h) End: 1010 0000 0100 ...
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Interrupt in 8085 microprocessor

What's the mechanism whereby the external device places a RST instruction on the bus, along with an interrupt # 0-7? I only know that external device sends signal to INTR pin to interrupt 8085
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What is the triggering level of INTR interrupt? [closed]

In the book we are told about the triggering level of other interrupts but I could not found any statements about the triggering level of INTR.please answer.
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How to reset all flags in 8085 without an arithmetic or logic operation?

How can I reset all flags in 8085 without an arithmetic or logic operation?
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In 8085, what is peripheral mapped I/O?

Is the peripheral mapped I/O different from what is known as port-mapped I/O or simply known as I/O mapped I/O? I don't see the usage of the term "peripheral mapped I/O" around much. Was it only ...