Questions tagged [actel]

Actel was a company that makes FPGAs. They are now part of Microsemi.

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What are the various files types in Actel (Microsemi) Libero?

While researching What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?, I found about various files types. But not all are defined in the Libero SoC or Design Constraints, ...
Brian Carlton's user avatar
4 votes
1 answer

What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?

This question is along the lines of What files/directories are needed to recreate a Xilinx PlanAhead project? but for an Actel/Microsemi FPGA design. I'm looking for a fairly standard design with ...
Brian Carlton's user avatar
2 votes
3 answers

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
Electronic_Nerd's user avatar
2 votes
2 answers

MicrosemiTools and C++

I've been trying to work with the Microsemi SmartFusion FPGA/MCU SOC boards and their "free" toolchain that includes an Eclipse-based "SoftConsole" IDE that appears to be based on the GNU C/C++ ...
Nate's user avatar
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TCL command in Libero SOC [Microsemi] to generate the IP cores

Does anybody knows the TCL command to generate the IP cores in a design for the Libero Soc tool of Microsemi (v11.4 SP1)? So the IP core (e.g. a FIFO) is configured and in the design. However, the ...
vermaete's user avatar
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HLS like programming on Actel devices

I have been using Xilinx FPGA devices for a while and I use HLS extensively to create parts of my design. I have currently switched to Actel FPGA devices and specifically the ProASIC3 family, and ...
abunickabhi's user avatar
0 votes
1 answer

Gate-level design with a Smartfusion2

I am working with a SmartFusion2 FPGA, and I am trying to implement a fine delay line. For that, I would like to control exactly the content of some LUTs, to get cells with no logic properties but ...
pserra's user avatar
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SmartFusion debug problems

I am using an Actel SmartFusion system-on-a-chip, running a bare-board application that uses the MSS with SPI, ACE and GPIO. (I am developing in Libero IDE 11.1 and SoftConsole.) My program ...
Stephen G's user avatar
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1 answer

PLL integrated CCC, Microsemi/Actel ProASIC3 nano Flash Family FPGA, A3P125

I have Micosemi/Actel ProASIC3 Nano A3P125,VQ100 Chip. I was looking for the PLL integrated CCC to connect 100MHz Clock and I have been through the manual ProASIC3 FPGA Fabric User’s Guide. where i ...
AlamPanah's user avatar
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compiling vhdl code

I have a source code written in VHDL wich is intended to make an FPGA communicate witch PC via UART and a 8051 microcontroller at the same time the FPGA will be connected to 8051 via data,adresse ...
furtsiv's user avatar