Questions tagged [activehdl]

Active-HDL is an integrated FPGA design creation and simulation solution produced by Aldec, Inc.

Filter by
Sorted by
Tagged with
-1
votes
1answer
28 views

Can propagation delays be simulated in Active-HDL?

I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function ...
0
votes
2answers
106 views

What kind of VHDL process is this?

This is from an example that comes with VUnit inside the array_axis_vcs fifo.vhd file. ...
0
votes
0answers
53 views

Importing foreign VHDL generic procedure with VHPI

I'm trying to learn the basics of VHPI (VHDL Procedural Interface) for linking my VHDL simulations to c++ code and have run into a bit of a snag. When I create a procedure with no generics (vhpi_Proc1)...
0
votes
0answers
32 views

What do small red lines in ActiveHDL waveform window signify?

Here is the waveform. In a few places for an input signal I can see that there are a few vertical red lines around some rising edge of clock. What do these lines mean? I have not synthesized this yet ...
3
votes
1answer
474 views

How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their ...
2
votes
2answers
284 views

digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge

I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this ...
2
votes
2answers
418 views

VHDL Simulation bug (am I losing it??)

I've got a simulation that simply takes an address as an input and 64 clock cycles later it simply outputs it on another port. For some reason, when I register the output data, it is not delayed by a ...
0
votes
1answer
321 views

Delta count overflow [duplicate]

I'm making JKnRnS master slave flip-flop, here is my code: ...
1
vote
1answer
291 views

Edge detector issue

I've a stupid problem and I don' figure out how I can solve it. In my design I'm using a rising edge detector. The problem is that ActiveHDL doesn't simulate it in the way that I expect. The VHDL code ...
6
votes
2answers
13k views

How do I build and use my own VHDL library?

I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a ...
3
votes
3answers
2k views

VHDL Error (Simple Expression Expected)

I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
8
votes
1answer
2k views

Why does this simple VHDL pattern for a shift register not work as expected

At first glance you would expect the VHDL source code below to behave as a shift register. In that q, over time would be ...