Questions tagged [activehdl]

Active-HDL is an integrated FPGA design creation and simulation solution produced by Aldec, Inc.

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What information does .lib file in ActiveHDL contain?

It seems that .lib can and does have different meanings. I am trying to understand the structure of ActiveHDL (simulator from Actel) .lib files. Here is an excerpt from the altera.lib ...
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318 views

How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their ...
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digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge

I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this ...
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384 views

VHDL Simulation bug (am I losing it??)

I've got a simulation that simply takes an address as an input and 64 clock cycles later it simply outputs it on another port. For some reason, when I register the output data, it is not delayed by a ...
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277 views

Delta count overflow [duplicate]

I'm making JKnRnS master slave flip-flop, here is my code: ...
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279 views

Edge detector issue

I've a stupid problem and I don' figure out how I can solve it. In my design I'm using a rising edge detector. The problem is that ActiveHDL doesn't simulate it in the way that I expect. The VHDL code ...
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How do I build and use my own VHDL library?

I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a ...
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VHDL Error (Simple Expression Expected)

I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
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Why does this simple VHDL pattern for a shift register not work as expected

At first glance you would expect the VHDL source code below to behave as a shift register. In that q, over time would be ...