Questions tagged [adder]
Digital circuits that adds values
275
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Reset Value in Register with Multiplexer [closed]
I have a very simple circuit that looks like this:
Every time the clock is pulsed, the value in the register is incremented by 1. However, I want to use a multiplexer so that when ...
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How to create a BCD to binary encoder that supports multi digit numbers using only logic gates [duplicate]
I've been thinking so long about how can I make a BCD to binary encoder that can encode BCD numbers like for example 11 or even 32767 into binary form (11 ---> 1011) but using only logic gates.
I ...
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How do I fix UUU output from modelsim testbench?
I am designing static Ram to be used with an add/sub on Quartus. I have created a block diagram and generated VHDL code. My schematic is correct but modelsim keeps giving me UUU for the output of my ...
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Dataflow operation on a variable is making it a don't care term (Verilog)
I want to implement a 4-bit parallel adder and subtractor using the same circuit while using a control input variable to switch between addition and subtraction. When my ...
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I am designing a Carry-Save Adder, but my output waveform is all StX
My CSA has ten 5-bit binary inputs, and one 9-bit output with a carry-out. I am trying to use full adder to realize the function. I have two 3 stages CSA to get two output sets (sum and count) and I ...
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I am designing a 4-bit Carry Look Ahead Adder, but it doesn't work correctly
I am new to Verilog. I am asked to write a gate-level design of a CLA adder. The equation is:
...
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How can I make addition in Verilog wraparound?
I'm creating an ALU in Verilog, and I would like overflow to be dealt with by wrapping around to lower values.
For example:
...
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Why isn't my addition in Verilog overflowing?
I'm testing a basic ALU in Vivado using a testbench.
One of my tests checks that overflow works correctly. The test has the following form:
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Is there single column Wallace tree?
I googled and learn the rules about Wallace tree.
If I understand right, wallace tree is designed to multiply. However, I want to know Is there single column wallace tree in the initial layer just to ...
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What is wrong with my 16 bit adder? How can I fix it?
I did this 16 bit adder in a simulator. Something is wrong. The automatic check returned FAIL. What did I do wrong? How can I fix it?
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74LS283 4-Bit Adder doesn't work as I expected. It sets some inputs to high voltage
I bought a few cheap 74LS283 chips. They don't work as I expected.
For some reason it sets the A1 pin to high voltage (5V) at all times. Considering the A1 and B1 pins are supposed to be input pins, ...
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How do we get a -1 in a 1-bit ALU?
In the 1-bit ALU and the table that is shown below, as you can see, the output is -1 when F0 = 1, F1 = 1, ENA = 0, ENB = 0, INVA = 1, INC = 0. The table is taken from a book (Structured Computer ...
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Adding voltage from multiple voltage dividers
I have the following schematic set up, where all of the resistances are known (I just didn't add them to the schematic as they should be irrelevant). If I read the voltage across the ground and the ...
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Where does the first carry-in go on a adder/subtractor circuit?
I am building a 4-bit adder/subtractor circuit using only logic gates on a breadboard. The following IC chips are being used:
XOR- 7486, AND - 7408, OR - 7432.
I have the full adders working fine. ...
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2
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Eight-bit full-adder carry light stays on high regardless of input
I am building a 8-bit full-adder circuit using the 7432 for the OR gate, the 7408 for the AND gate, and the 7486 for the XOR gate. I am only on the first bit and I am already having problems.
Problem:
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Regarding the Static Full Adder Circuit
As per the book on Digital Integrated Circuits by Rabaey Et al. in the static CMOS implementation of Full adder circuit with Co= carry out and S= Sum
As mentioned in the marked point of the attached ...
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Similarity in "carry and sum" and "difference and borrow"
i know carry and sum from all the sources i studied in YT (particularly KNOWLEDGE GATE) except neso academy that teaches using difference and borrow in same place as carry and sum
Sources:-
Knowledge ...
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Digital Design - Reduction Operator
How do I build an 7-bit reduction operator (i.e. a device counts the number of 1s in the input) ?
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Excess-3 adder in Verilog
I am trying to code an Excess-3 Adder with two 12-bit inputs and a 16 m-bit output. The thing is that there are some restrictions, basically "anything that might make our work easier".
These ...
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Simplifying addition of three bits from using three half-adders
I analysed using three half-adders to add three (same weight) binary digits.
I understood that the third half-adder's and gate will never give an output different from 0 so we used two half-adders and ...
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How to fix the include statement error in Verilog testbench code?
I implemented the four-bit ripple carry adder using Verilog. However, I did not understand why the compiler generated this error
Include file FBaddsub.v not found No top level modules, and no -s
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What is the propagation delay of a carry save adder?
I was reading this paper about the Comparison of Adder Topologies, when I came across a page talking about the Carry Save Adder. They say on page 3:
The propagation delay is 3 gates regardless of the ...
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What is the best adder to use inside a FPU unit?
I have this college assignment where I was asked to implement a FPU (floating point unit) that adds numbers using only Verilog, but that's not a problem here.
The problem is that I must use a 32-bit ...
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Digital signals - multiplication of Bits ( number of bits ) - How to do it? ( binary bits ) [closed]
Let us say I have a number with p bits:
x = [___...___] >> p Bits.
and I want to multiply it by another p bits.
will I receive:
...
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3
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Passive voltage adder
I have two outputs of a voltage source that do ±10 V with 16 bit. This leads to a theoretical resolution of a bit step of 0.3 mV. My goal is to have more resolution by using a voltage divider of 100 ...
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Why does adding "& 1" to an assign statement produce a completely different synthesis?
I am trying to implement a one-bit full adder in Verilog. Here's my original code:
...
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Delay of ripple carry adder
I denote delay timing as "@ value". As you can see the picture above, C_in0(carry in 0), A0(input A's 0th bit), and B0 are initially ready so there is no delay which means they all have @0 ...
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Is there a way of converting easily binary numbers to its ASCII equivalent?
I have this digital circuit design problem where we receive two two-digits numbers in ASCII, I have to convert them to binary, add them, and the result I have to encode it to ASCII again.
I actually ...
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Carry bypass adder delay higher than expected with timing analysis
Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...
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Tensor core makeup
I understand that a normal CPU works through adder circuits in their cores.
Is a gpu core still based on adder circuits with a different instruction set or is it physicaly a different circuit?
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Why do we implement adders via serial full adders as opposed to an optimized logic circuit?
In my little time studying digital systems, it seems that textbooks immediately jump to the fact that we implement adders via serial (i.e. the chaining together of) full adders. It's not a priori ...
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Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?
The book But How Do It Know? presents an 8-bit computer architecture in which arithmetic-logic instructions (that is, instructions which are executed by the ALU) have 1 as the most significant bit, ...
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Is it mandatory to sign-extend when adding two different-sized buses?
I am trying to optimize a critical path in my design. The bottle-neck of the path is a 32-bit ADDER between a 32-bit bus and a sign-extended 16-bit bus. At first, when I didn't realize it was signed, ...
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I am unable to figure out how the answer to following question is 70ns
Here's the question:
Each full adder has 2 AND gates 2 XOR and 1 OR gate so carry propagation delay for each full adder should be 80 ns by the data provided and as there are 4 full adders, so shouldn'...
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Verilog code for adder shows unknown results (X) for some reason
I wrote this code, and it doesn't give a known value for the sum (S[15:0] in the waveforms). Why is that?
Design:
...
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Minimizing delay of Full Adder
It is said that by exploiting the inverting property we can "reduce one inverter delay in each full adder". Why is that?
Clearly, we can reduce one for the input of the first adder, but we ...
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Inversion property of full adder
The given inverting property states that the FA stays the same if I invert all the inputs and outputs.
Using this idea we modify the ripple carry adder into the below form, but why can it be ...
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Full adder Cout expression issue
The truth table of a full adder is as below.
Cout is given as Cout = AB + Cin(A XOR B).
not sure why is that because when I do my k-map on the Cout, I get Cout = AB + Cin(A+B).
does anyone know why is ...
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Carry-select adder - Time calculation
a) Suppose a binary pick-up adder (carry-select) of 32-bits, comprising 4 sub-sections adders spreading carry of range 8 bits. Show the values obtained internally in the circuit of this adder to ...
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Does a 64-bit computer require 64 full adders to perform additions/subtractions, or would it somehow require less?
I have seen online these diagrams for 4-bit adders which feature 4 individual full adders chained together with the carry out from the previous feeding into the carry in to the next.. Likewise, to add ...
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Building an 8-bit adder/subtractor using two 4-bit adder/subtractors and the result has a difference of 16 for values above 16
I'm trying to build an 8-bit adder/subtractor using two 4-bit adder/subtractors
The result is always 16 below the required value when adding two numbers above 16 and 16 above the required value when ...
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Bits are toggled in step 1 or 9's complement is done using subtraction?
In base 2, I want to subtract x-y using adder. Where, x = (1011)2 and y = (0101)2
[For verification, in decimal x=(11)10, y = (5)10. So, we are seeking (6)10 as the answer ]
In base 2 using adder we ...
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Carry Skip (Bypass) Adder wcs vs Crit. Path
I'm studying adder types and, as the title says, I'm having a problem with the carry-skip.
From what I know the critical path of an equal blocks carry-skip adder is supposed to go from the LSB of the ...
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Additional bits computation in VHDL
Given an array of N elements, element is M bits vector. I am going to sum them up.
For example, given an array of 12 bits vectors.
...
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What is wrong with my 2 bit adder? [closed]
I'm trying to make a 2 bit adder in Logism. I made a half adder and a full adder chained together. Some equations work, and some don't. I'm using the structure that I see everywhere on how to make an ...
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How to capture output of adder?
I am experimenting with a circuit for adding two numbers represented by two digital counters and two cascaded 4 bits adders (74HC283). I tested separately with cascaded 74HC163 and with asynchronous ...
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How to use a 32-bit adder to add two 16-bit numbers?
How can I add two 16-bit numbers using a 32-bit adder?
The 32-bit adder takes one cycle to add two numbers. How can I add "p+q" and "r+s" (16-bit numbers) in one cycle?
Note: The ...
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Transistor full adder circuit [duplicate]
I'm building a full adder circuit using transistors. I am only doing it for fun, that's why I'm not using IC gates.
I am feeding it 5V and I'm getting really strange outputs. And it isn't even ...
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How do I create a 1-bit full adder that outputs a 2-bit sum?
I am trying to build a 1-bit full adder that outputs a 2-bit sum.
I know that the standard 1-bit FA outputs a 1-bit sum and a carry bit, but I was wondering how can I modify the FA such that the carry ...
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