Questions tagged [adder]
Digital circuits that adds values
181
questions
0
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2answers
51 views
How does carry in work in full adders?
Yesterday I asked a similar question and realized I still don't quite get it, so I'm sorry about that.
Here is explicitly what I mean:
This is a part of a full adder. The first row in which ...
0
votes
4answers
57 views
binary addition / truth table?
I'm trying to understand how binary addition works.
If I understand it correctly, with two variables e.g. x and y you add a ...
0
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1answer
87 views
Efficiently calculate \$-x-y\$ using a single adder
I would like to know if there is an efficient way of implementing the operation \$-x-y\$ on an FPGA using only a single chain of adders or subtractors, roughly equal in length to the maximum number of ...
2
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3answers
72 views
How does a “standard” ripple carry adder behave?
I came across the following problem:
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is ...
1
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1answer
30 views
Relative difficulty between leading zero counting and addition
Consider a 32-bit or 64-bit ALU that must implement both count leading zeros and integer addition, with low latency (say a few cycles), implemented on a modern high frequency logic process.
Which is ...
1
vote
1answer
51 views
2's Complement 4 Bit adder. (Multisim)
I am hoping I am doing something dumb here. I know there are other posts about this but everything I have found leads me to believe my circuit should be working. Yes this is for homework. No, I am not ...
0
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0answers
21 views
ripple-borrow binary subtraction circuit
How does this patented ripple-borrow binary subtraction circuit eliminate the need for doing two-complement conversion on the input, thus saves on hardware circuit computation area and time ?
0
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2answers
60 views
simple six-position voting machine into a 7 position voting machine
I'm new to learning about full and half adders and what not. but I am struggling to understand this question out of my study manual.
The pictures shows a simple six-position voting machine module ...
-1
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1answer
38 views
What is the purpose of carry-in in full adder? If carry in equals carry out of previous adder, then I have question
In 5th row carry out is 0 then why is carry-in equal to 1 in next adder?
0
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0answers
27 views
Propagation delay in full adder models
From my last question Propgation delay
I tried to solve for the time delay that occurs at the last carry
Not sure if I have done it right .. Please correct me if I m wrong
0
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0answers
74 views
VHDL - How to add several numbers parallel
i would like to add several (variable number N, fixed size) numbers in VHDL. In the image below you see how i want to do the additions. In this example there are N=6 numbers (A0 - A5). I have a ...
-1
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1answer
108 views
FPGA too slow for my ripple carry adder?
I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
0
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1answer
52 views
0
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1answer
51 views
3 bit full adder designing
I am new to the concepts of using adders to add numbers but I tried using the definitions which I understood as given two binary digits A, B the full adder takes three inputs A, B, C where C acts as a ...
0
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2answers
62 views
Full Adder Circuit
This circuit is based around the SN74HC283 4 bit full adder.
What purpose does the resistor network serve?
Will this circuit work without any resistors, i.e. using raw inputs and outputs?
...
0
votes
2answers
39 views
Instantiating modules in SystemVerilog
This is a picture of a system that I am building:
(original)
I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
0
votes
1answer
297 views
Implementing a 4-bit ripple carry adder/subtractor using structural VHDL
I have to create a 4-bit ripple carry adder/subtractor. The circuit will have two 4-bit data inputs (A and B), a control line (Add/Sub), a 4-bit data outputs (S) and a carry out bit (Cout).
I have ...
0
votes
1answer
34 views
Parallel Prefix Adder explained
I think I have understood Carry Lookahead adders.
However, I don't really understand how parallel prefix adders evolve from carry lookaheads. Can someone explain to me the difference between PPA and ...
0
votes
1answer
149 views
Verilog counter made of 32 bit adder (syntax error)
For a school assignment I have to make a counter, based on a 32-bit adder, that increments with 1 every clockcycle if 'enable = high' and 'reset = low'.
When I try to use the adder in my counter ...
0
votes
1answer
90 views
problem with 6 bit adder
I am working on Subtractor circuits using Adder circuits. I have to do x-y.
Suppose x = 111111 , y = 100000
Using the 6 bit adder circuit I created the overflow flag is coming to be 0 but when I ...
0
votes
1answer
266 views
Converting full adder to subtractor using inverter
I've been trying to convert a full adder to a full subtractor using an inverter.
I tried using not gates at the B input ( in A B Cin ) and also using it in the outputs but the final answers are not ...
0
votes
0answers
124 views
Designing Excess 5 to BCD using Binary parallel adder
I've been trying to form a combinational logic circuit of converting excess 5 to BCD. I've been able to make a normal logic circuit but I do not know what a binary parallel adder is.
My attempt - ...
0
votes
1answer
199 views
4-Bit Adder Subtractor Quartus Prime Lite
I designed a 4-bit adder/subtractor circuit in Quartus Prime Lite. I am struggling with getting the correct output on the waveform. It is supposed to take the unsigned decimal numbers and add or ...
-2
votes
3answers
127 views
Why does a full adder need an OR gate?
I have read and I understand how the full adder works (or atleast I think I do :D). It combines two half adders and either one of them can have a carry over, hence the OR gate. But why do we need ...
0
votes
1answer
292 views
About the critical path of ripple adder
I have trouble understanding what's critical path delay of n-bit Ripple Carry Adder. In the book I read, given N-bit Ripple Carry Adder formed from N single 1-bit full adder:
the critical path ...
0
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1answer
118 views
Adding multiple differential signal
As I asked in "Adding multiple analog signal" before, I got that: for adding some signal together, we can only use op-amp, instead of lovely integrated circuit (ough).
But the question arise because ...
0
votes
2answers
92 views
Adding multiple analog signal
I'm trying to add 4 output of ADA8282 together and create only one analog signal with bandwidth about 6 MHz, I know Op-Amp adder as "How can I add three AC signals?" and "ElectronicTutorial" said. ...
0
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1answer
223 views
How do I make a double dabble circuit with logic gates
Im attempting to make a 8 bit binary calculator that displays on multiple seven segment displays. Can double dabble be done with logic gates. If so, how?
0
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2answers
33 views
Doubt about half adder timing
In my book there is the architecture of a basic circuit with a half adder with 1 AND and 1 XOR for the carry, and a "maimed" half adder with one XOR for the previous carry. Then book say that minimum ...
-2
votes
1answer
2k views
Difference between Full Adder, Parallel Adder and Ripple Carry Adder?
I am a student and i cannot find any prominent difference between the full adder, parallel adder and ripple carry adder. The full adder for n-bit number requires n full adder cascaded, so as the ...
1
vote
0answers
41 views
How do I draw the truth table of an adder/subtractor that sets flags, and those flags are the inputs of a comparator?
How do I draw a truth table of a circuit that :
starts off with a full adder/subtractor
outputs the result F based on the two inputs (add if opcode is 0, subtract if opcode is 1)
then output three ...
0
votes
2answers
160 views
Compare two numbers of four bits
I have two numbers both with four bits (a3 to a0 and b3 to b0 reading from left to right) and I would like to find out if a is bigger than b.
I have drawn a solution of mine and a short mathematical ...
0
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1answer
342 views
Some questions about Carry-lookahead adder and Ripple-Carry Adder
I was reading about the Carry-lookahead adder and about the Ripple-Carry Adder. I saw some designs and it made me wonder the following questions:
Both questions are the same for both adders so i'll ...
1
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1answer
887 views
Formulas for Carry out in a Full Adder
Given a full adder with inputs $$A, B \text{ and } C_{in}$$
The formulas for the outputs are $$S = A \oplus B \oplus C_{in} \text{ , Where } \oplus \text{means XOR}$$ and $$C_{out} = AB + AC_{in} + ...
-2
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1answer
1k views
Trouble with 8-bit Carry Lookahead Adder in Verilog
I'm new to Verilog programming. I'm trying to work up to a 64-bit CLA by building a 4-bit CLA, then an 8-bit (out of 2 instances of a 4-bit), then a 16-bit (out of 2 instances of the 8-bit one). I'll ...
1
vote
1answer
125 views
CMOS Adder circuits
I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill ...
0
votes
1answer
42 views
Is parallel adder doing additions in each bit position simultaneously?
Does parallel binary adder actually make additions in each position simultaneously? I have read various sources and they all have this description relating to the parallel binary adder: "The additions ...
0
votes
1answer
47 views
Alternative for adder out of NAND-gates
Recently I was experimenting with the NAND-gate representation of an adder circuit and tried to implemenent it without crossing wires. So I got this:
The carry is negated, but when chaining two of ...
0
votes
1answer
754 views
What is the formula for calculating out the time delay for the sum output in a ripple-carry adder circuit? [closed]
I am amidst writing up calculations for electronics research, but am unsure how to calculate the time delay for the sum output. I am needing to calculate the time-delay for the sum and carry outputs ...
-3
votes
2answers
76 views
Do we have binary dividers cicuit on cisc computer? [duplicate]
Just like we have binary multipler circuit in cisc computer so do we have binary divider circuit in cisc computer? Or it is just like we use algothrims instead of having a real divider circuit? (Just ...
-1
votes
1answer
76 views
Add two voltage signal and Convert output to current signal
I generated two different Signals using DDS and now I want to add them and convert output signal to current signal without any distortion in it? what is the best and accurate part I can use ?
1
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1answer
222 views
Serial adder using one's complement arithmetic
The Apollo Guidance Computer (AGC) used one's complement arithmetic. The following clip from Frank O'Brien's book on the Apollo Guidance Computer (2010) offers a partial justification for this ...
0
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1answer
377 views
Can we form any circuit using half adders only? (assuming we have as many half adders as we want)
Using various combinations on half adders I get these outputs:
{0,1,1,0},{0,0,0,1},{0,0,0,0},{0,1,1,1}
And I also know that we can form any gets using NAND ...
0
votes
1answer
615 views
using generate statement in verilog
I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog
this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
0
votes
1answer
381 views
Ripple carry adder doubt
In a 4 bit ripple carry adder 4 full adders are connected serially, one FA waits for the carry input from the previous FA. My question is, when calculating the propagation delay, should we assume that ...
-1
votes
1answer
82 views
Is it important to add a transistor for the output of a 4 bit adder [closed]
Is it necessary to add an transistor to the output of my four bit adder. I want to add an led to show the 5 bit output. Should I add a transistor or or just directly connect the led’s anode to the ...
0
votes
1answer
424 views
best and worst-case delay of an adder
I have designed a 32-bit adder using a hierarchical carry look-ahead design. I'm now trying to run a spice simulation of this adder and am wondering what inputs will provide the best and worst-case ...
7
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3answers
1k views
check if an unsigned binary number is divisible by 15
I'm a computer science student and I got stuck on this question for hours.
We have a binary unsigned number X, represented by 12 bits.
We would like to build a system with 1 bit output - Y, that will ...
1
vote
1answer
67 views
Combinational Linear Shifting VHDL
I am designing a 32 bit floating point pipelined and synthesizable adder/multiplier as part of group for a class in school. I was put in charge of the re-normalization. Part of this is left or right ...
1
vote
1answer
2k views
Propagation delay in full adder
I'm dealing with a question about an implementation of a full adder with component delays.
tpd(XOR) = 5 ns
tpd(AND) = 2 ns
tpd(OR) = 2 ns
I'm having problems solving for the the propagation delay ...
