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Questions tagged [adder]

Digital circuits that adds values

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1answer
37 views

What is the purpose of carry-in in full adder? If carry in equals carry out of previous adder, then I have question

In 5th row carry out is 0 then why is carry-in equal to 1 in next adder?
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0answers
21 views

Propagation delay in full adder models

From my last question Propgation delay I tried to solve for the time delay that occurs at the last carry Not sure if I have done it right .. Please correct me if I m wrong
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0answers
64 views

VHDL - How to add several numbers parallel

i would like to add several (variable number N, fixed size) numbers in VHDL. In the image below you see how i want to do the additions. In this example there are N=6 numbers (A0 - A5). I have a ...
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1answer
97 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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1answer
35 views

Full Adder driven by clock [FPGA/VHDL]

I've got Ripple Carry adder (26bit) made from scratch. ...
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1answer
45 views

3 bit full adder designing

I am new to the concepts of using adders to add numbers but I tried using the definitions which I understood as given two binary digits A, B the full adder takes three inputs A, B, C where C acts as a ...
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2answers
49 views

Full Adder Circuit

This circuit is based around the SN74HC283 4 bit full adder. What purpose does the resistor network serve? Will this circuit work without any resistors, i.e. using raw inputs and outputs? ...
0
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2answers
35 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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1answer
226 views

Implementing a 4-bit ripple carry adder/subtractor using structural VHDL

I have to create a 4-bit ripple carry adder/subtractor. The circuit will have two 4-bit data inputs (A and B), a control line (Add/Sub), a 4-bit data outputs (S) and a carry out bit (Cout). I have ...
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1answer
26 views

Parallel Prefix Adder explained

I think I have understood Carry Lookahead adders. However, I don't really understand how parallel prefix adders evolve from carry lookaheads. Can someone explain to me the difference between PPA and ...
0
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1answer
104 views

Verilog counter made of 32 bit adder (syntax error)

For a school assignment I have to make a counter, based on a 32-bit adder, that increments with 1 every clockcycle if 'enable = high' and 'reset = low'. When I try to use the adder in my counter ...
0
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1answer
66 views

problem with 6 bit adder

I am working on Subtractor circuits using Adder circuits. I have to do x-y. Suppose x = 111111 , y = 100000 Using the 6 bit adder circuit I created the overflow flag is coming to be 0 but when I ...
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1answer
157 views

Converting full adder to subtractor using inverter

I've been trying to convert a full adder to a full subtractor using an inverter. I tried using not gates at the B input ( in A B Cin ) and also using it in the outputs but the final answers are not ...
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0answers
104 views

Designing Excess 5 to BCD using Binary parallel adder

I've been trying to form a combinational logic circuit of converting excess 5 to BCD. I've been able to make a normal logic circuit but I do not know what a binary parallel adder is. My attempt - ...
0
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1answer
162 views

4-Bit Adder Subtractor Quartus Prime Lite

I designed a 4-bit adder/subtractor circuit in Quartus Prime Lite. I am struggling with getting the correct output on the waveform. It is supposed to take the unsigned decimal numbers and add or ...
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3answers
110 views

Why does a full adder need an OR gate?

I have read and I understand how the full adder works (or atleast I think I do :D). It combines two half adders and either one of them can have a carry over, hence the OR gate. But why do we need ...
0
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1answer
232 views

About the critical path of ripple adder

I have trouble understanding what's critical path delay of n-bit Ripple Carry Adder. In the book I read, given N-bit Ripple Carry Adder formed from N single 1-bit full adder: the critical path ...
0
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1answer
103 views

Adding multiple differential signal

As I asked in "Adding multiple analog signal" before, I got that: for adding some signal together, we can only use op-amp, instead of lovely integrated circuit (ough). But the question arise because ...
0
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2answers
77 views

Adding multiple analog signal

I'm trying to add 4 output of ADA8282 together and create only one analog signal with bandwidth about 6 MHz, I know Op-Amp adder as "How can I add three AC signals?" and "ElectronicTutorial" said. ...
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1answer
153 views

How do I make a double dabble circuit with logic gates

Im attempting to make a 8 bit binary calculator that displays on multiple seven segment displays. Can double dabble be done with logic gates. If so, how?
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2answers
32 views

Doubt about half adder timing

In my book there is the architecture of a basic circuit with a half adder with 1 AND and 1 XOR for the carry, and a "maimed" half adder with one XOR for the previous carry. Then book say that minimum ...
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1answer
2k views

Difference between Full Adder, Parallel Adder and Ripple Carry Adder?

I am a student and i cannot find any prominent difference between the full adder, parallel adder and ripple carry adder. The full adder for n-bit number requires n full adder cascaded, so as the ...
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0answers
40 views

How do I draw the truth table of an adder/subtractor that sets flags, and those flags are the inputs of a comparator?

How do I draw a truth table of a circuit that : starts off with a full adder/subtractor outputs the result F based on the two inputs (add if opcode is 0, subtract if opcode is 1) then output three ...
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2answers
147 views

Compare two numbers of four bits

I have two numbers both with four bits (a3 to a0 and b3 to b0 reading from left to right) and I would like to find out if a is bigger than b. I have drawn a solution of mine and a short mathematical ...
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1answer
315 views

Some questions about Carry-lookahead adder and Ripple-Carry Adder

I was reading about the Carry-lookahead adder and about the Ripple-Carry Adder. I saw some designs and it made me wonder the following questions: Both questions are the same for both adders so i'll ...
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1answer
742 views

Formulas for Carry out in a Full Adder

Given a full adder with inputs $$A, B \text{ and } C_{in}$$ The formulas for the outputs are $$S = A \oplus B \oplus C_{in} \text{ , Where } \oplus \text{means XOR}$$ and $$C_{out} = AB + AC_{in} + ...
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1answer
1k views

Trouble with 8-bit Carry Lookahead Adder in Verilog

I'm new to Verilog programming. I'm trying to work up to a 64-bit CLA by building a 4-bit CLA, then an 8-bit (out of 2 instances of a 4-bit), then a 16-bit (out of 2 instances of the 8-bit one). I'll ...
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1answer
92 views

CMOS Adder circuits

I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill ...
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1answer
42 views

Is parallel adder doing additions in each bit position simultaneously?

Does parallel binary adder actually make additions in each position simultaneously? I have read various sources and they all have this description relating to the parallel binary adder: "The additions ...
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1answer
45 views

Alternative for adder out of NAND-gates

Recently I was experimenting with the NAND-gate representation of an adder circuit and tried to implemenent it without crossing wires. So I got this: The carry is negated, but when chaining two of ...
0
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1answer
708 views

What is the formula for calculating out the time delay for the sum output in a ripple-carry adder circuit? [closed]

I am amidst writing up calculations for electronics research, but am unsure how to calculate the time delay for the sum output. I am needing to calculate the time-delay for the sum and carry outputs ...
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2answers
68 views

Do we have binary dividers cicuit on cisc computer? [duplicate]

Just like we have binary multipler circuit in cisc computer so do we have binary divider circuit in cisc computer? Or it is just like we use algothrims instead of having a real divider circuit? (Just ...
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1answer
73 views

Add two voltage signal and Convert output to current signal

I generated two different Signals using DDS and now I want to add them and convert output signal to current signal without any distortion in it? what is the best and accurate part I can use ?
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1answer
198 views

Serial adder using one's complement arithmetic

The Apollo Guidance Computer (AGC) used one's complement arithmetic. The following clip from Frank O'Brien's book on the Apollo Guidance Computer (2010) offers a partial justification for this ...
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1answer
310 views

Can we form any circuit using half adders only? (assuming we have as many half adders as we want)

Using various combinations on half adders I get these outputs: {0,1,1,0},{0,0,0,1},{0,0,0,0},{0,1,1,1} And I also know that we can form any gets using NAND ...
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1answer
521 views

using generate statement in verilog

I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
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1answer
362 views

Ripple carry adder doubt

In a 4 bit ripple carry adder 4 full adders are connected serially, one FA waits for the carry input from the previous FA. My question is, when calculating the propagation delay, should we assume that ...
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1answer
81 views

Is it important to add a transistor for the output of a 4 bit adder [closed]

Is it necessary to add an transistor to the output of my four bit adder. I want to add an led to show the 5 bit output. Should I add a transistor or or just directly connect the led’s anode to the ...
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1answer
413 views

best and worst-case delay of an adder

I have designed a 32-bit adder using a hierarchical carry look-ahead design. I'm now trying to run a spice simulation of this adder and am wondering what inputs will provide the best and worst-case ...
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3answers
1k views

check if an unsigned binary number is divisible by 15

I'm a computer science student and I got stuck on this question for hours. We have a binary unsigned number X, represented by 12 bits. We would like to build a system with 1 bit output - Y, that will ...
1
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1answer
60 views

Combinational Linear Shifting VHDL

I am designing a 32 bit floating point pipelined and synthesizable adder/multiplier as part of group for a class in school. I was put in charge of the re-normalization. Part of this is left or right ...
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1answer
2k views

Propagation delay in full adder

I'm dealing with a question about an implementation of a full adder with component delays. tpd(XOR) = 5 ns tpd(AND) = 2 ns tpd(OR) = 2 ns I'm having problems solving for the the propagation delay ...
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1answer
867 views

4ِ-bit adder in Multisim

I want to design a 3-bit by 3-bit number adder circuit. The result must be in BCD. And I want to show the result by using 7-segment displays. I built this circuit. I'm not sure from it, and when I ...
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1answer
76 views

What's wrong with my logic in my adder-subtractor?

I'm trying to create an adder-subtracter using only one adder, not gate, and multiplexer. When A = 1000, B = 0001 it results in Q = 0111. If my math is right, that is 8 +(-1) = 7 and 7 = 0111 which is ...
0
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1answer
36 views

Adder propagate P expression [closed]

When dealing with carry-look-ahead adders, the following expressions are commonly used: $$P=A \oplus B$$ or $$P = A + B$$ I understand that using the second expression takes less gates for calculating ...
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2answers
352 views

Question about 4-bit binary adder on 7 segment display and subtraction

In my lab, we successfully built a 4-bit binary parallel adder and were able to display the results of some tests on the 7 segment display. But our TA asked us to try something: subtract 1-9, and we ...
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1answer
140 views

Computing a mathematical expression using half and full adders

I am new to logical desing and I am not sure how to start the exercise. The problem: Assume that we have 2 assinged numbers of 2 bits (A = a1 a0 and B = b1 b0). Desing a combinational logical ...
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0answers
251 views

Latency of Components

Latency comparison between the addition of dependent modules vs independent modules? For example, a 32-bit adder made up of thirty-two 1-bit adders. Each 1-bit adder calculation depends on the ...
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2answers
395 views

Gate delay of carry out C and sum S in ripple carry adder

Question How to find the gate delay of carry out \$C_{n}\$ and sum \$S_{n}\$ in ripple carry adder? I encountered this doubt while going through the book by Carl Hamacher. It is written as: ...
14
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1answer
555 views

Parallel prefix adder cells in Negabinary

I'm trying to design a parallel prefix adder for a negabinary based adder. Negabinary is base \$-2\$ instead of the familiar base \$2\$ binary. Each 1 bit adder generates a sum and two (instead of one ...