Questions tagged [adder]
Digital circuits that adds values
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Why does adding "& 1" to an assign statement produce a completely different synthesis?
I am trying to implement a one-bit full adder in Verilog. Here's my original code:
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Delay of ripple carry adder
I denote delay timing as "@ value". As you can see the picture above, C_in0(carry in 0), A0(input A's 0th bit), and B0 are initially ready so there is no delay which means they all have @0 ...
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Adder and Shifter in Digital Electronics
Using only adders and shifters, perform the following 8-bit arithmetic operations. Assume A and B are 8-bit 2’s complement number.
a. 28 x A - 53 x B
b. A/8 + 32 x B
My effort:
Firstly, I convert 28 ...
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Adder optimised with hardcoded constant
I've been reviewing Intel's paper Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC where they claim to have a completion adder optimised with a hardcoded constant that is unique ...
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VHDL - using PORT MAP with FOR LOOP?
Just touching base on one thing. My group and I are making a stopwatch with a lap function for our final project. For the lap function we are using a ROM along with three 32-bit subtractors, which use ...
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Is there a way of converting easily binary numbers to its ASCII equivalent?
I have this digital circuit design problem where we receive two two-digits numbers in ASCII, I have to convert them to binary, add them, and the result I have to encode it to ASCII again.
I actually ...
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1-bit Full Adder is a universal gate, like NAND gate? [closed]
I want to know if a 1-bit Full Adder can be considered a universal gate.
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Carry bypass adder delay higher than expected with timing analysis
Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...
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Tensor core makeup
I understand that a normal CPU works through adder circuits in their cores.
Is a gpu core still based on adder circuits with a different instruction set or is it physicaly a different circuit?
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Why do we implement adders via serial full adders as opposed to an optimized logic circuit?
In my little time studying digital systems, it seems that textbooks immediately jump to the fact that we implement adders via serial (i.e. the chaining together of) full adders. It's not a priori ...
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Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?
The book But How Do It Know? presents an 8-bit computer architecture in which arithmetic-logic instructions (that is, instructions which are executed by the ALU) have 1 as the most significant bit, ...
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Is it mandatory to sign-extend when adding two different-sized buses?
I am trying to optimize a critical path in my design. The bottle-neck of the path is a 32-bit ADDER between a 32-bit bus and a sign-extended 16-bit bus. At first, when I didn't realize it was signed, ...
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I am unable to figure out how the answer to following question is 70ns
Here's the question:
Each full adder has 2 AND gates 2 XOR and 1 OR gate so carry propagation delay for each full adder should be 80 ns by the data provided and as there are 4 full adders, so shouldn'...
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Minimizing delay of Full Adder
It is said that by exploiting the inverting property we can "reduce one inverter delay in each full adder". Why is that?
Clearly, we can reduce one for the input of the first adder, but we ...
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Inversion property of full adder
The given inverting property states that the FA stays the same if I invert all the inputs and outputs.
Using this idea we modify the ripple carry adder into the below form, but why it can be ...
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Full adder Cout expression issue
The truth table of a full adder is as below.
Cout is given as Cout = AB + Cin(A XOR B).
not sure why is that because when I do my k-map on the Cout, I get Cout = AB + Cin(A+B).
does anyone know why is ...
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Carry-select adder - Time calculation
a) Suppose a binary pick-up adder (carry-select) of 32-bits, comprising 4 sub-sections adders spreading carry of range 8 bits. Show the values obtained internally in the circuit of this adder to ...
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Does a 64-bit computer require 64 full adders to perform additions/subtractions, or would it somehow require less?
I have seen online these diagrams for 4-bit adders which feature 4 individual full adders chained together with the carry out from the previous feeding into the carry in to the next.. Likewise, to add ...
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Building an 8-bit adder/subtractor using two 4-bit adder/subtractors and the result has a difference of 16 for values above 16
I'm trying to build an 8-bit adder/subtractor using two 4-bit adder/subtractors
The result is always 16 below the required value when adding two numbers above 16 and 16 above the required value when ...
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Bits are toggled in step 1 or 9's complement is done using subtraction?
In base 2, I want to subtract x-y using adder. Where, x = (1011)2 and y = (0101)2
[For verification, in decimal x=(11)10, y = (5)10. So, we are seeking (6)10 as the answer ]
In base 2 using adder we ...
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Carry Skip (Bypass) Adder wcs vs Crit. Path
I'm studying adder types and, as the title says, I'm having a problem with the carry-skip.
From what I know the critical path of an equal blocks carry-skip adder is supposed to go from the LSB of the ...
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Additional bits computation in VHDL
Given an array of N elements, element is M bits vector. I am going to sum them up.
For example, given an array of 12 bits vectors.
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What is wrong with my 2 bit adder? [closed]
I'm trying to make a 2 bit adder in Logism. I made a half adder and a full adder chained together. Some equations work, and some don't. I'm using the structure that I see everywhere on how to make an ...
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How to capture output of adder?
I am experimenting with a circuit for adding two numbers represented by two digital counters and two cascaded 4 bits adders (74HC283). I tested separately with cascaded 74HC163 and with asynchronous ...
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Arithmetic - Absolute value
I constructed a circuit that calculates the absolute value of a signed 4-bit number in two's complement
Then the second question of the exercise was to show the correctness of my circuit using the ...
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Transistor full adder circuit [duplicate]
I'm building a full adder circuit using transistors. I am only doing it for fun, that's why I'm not using IC gates.
I am feeding it 5V and I'm getting really strange outputs. And it isn't even ...
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How do I create a 1-bit full adder that outputs a 2-bit sum?
I am trying to build a 1-bit full adder that outputs a 2-bit sum.
I know that the standard 1-bit FA outputs a 1-bit sum and a carry bit, but I was wondering how can I modify the FA such that the carry ...
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How to reason about this 'adder with memory' circuit?
I'm reading through "Code" by Charles Petzold and I had a question about the following circuit illustrated in the book:
Let's assume that the latches in the 16-bit counter and the 8-bit ...
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Time (Propagation delay) taken for adding 3 n-bit binary numbers using Carry Propagate Adders (Ripple carry adders)
While being introduced to carry save addition technique, I was told that the time taken for adding 3 n-bit binary numbers using ripple carry adders will be (2n+1)t_FA (Assuming we neglect the minor ...
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Designing lookup table(LUT) for half adder in FPGA
I want to implement half adder using FPGA. For this I need to design CLB, more specifically LUT for half adder. I know LUT gives only one output. But, for half adder we get two output. One for sum and ...
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Building a better staged 1's complement adder tree?
I'm trying to calculate the checksum of IPv4 and UDP messages coming out of my Ethernet controller module. The checksum calculation for both IPv4 and UDP is defined as 1's complement addition, which ...
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Convert from 4 bit binary number to 2 bit binary number
I am currently using logisim to output a 2 bit binary number, however, the bit adder releases 4 bit binary number instead. Is there any way to fix this? (I am currently using v 2.14.6 .)
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Given 4 inputs (A,B,C,D) how can I design a circuit that counts the number of 1s?
The question is in the title.
If I have 4 inputs, how can I count the number of 1s using full/half adders and produce the binary equivalent of how many 1s exist in the 4 inputs?
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Full adder 2D addressing
I try to implement a full adder circuit using square arrays.
I've used Digital software to design it. Also I've tested it. It works fine.
But my implementation is quite different from the circuit ...
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Overflow in Adder Circuits
We were learning about full adder and half adder circuits and how overflow might occur in them. My professor told that for a full adder of n bits the range is [-2^(n-1) , 2^(n-1)-1]. What I don't get ...
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Simplify the boolean function $$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$
I want to simplify the following boolean function:
$$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$
Here's my attempt:
\begin{align}
Z &= A\bar B \bar{C_i} + \bar A B ...
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What parts/sections of a CPU take the biggest number of transistors?
I was surprised to hear CPUs only have a number of ALUs. What are most of the transistors in a CPU dedicated to?
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How can I generate overflow condition from a 74'283 or 74'181 adder without an output pin of the carry-in of the MSB?
I've been building my own CPU from low level chips, using the 74LS283 adder. And I've been wondering about how to set the overflow flag. Finally I seem to have grasped that the overflow flag is the ...
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3-to-2 line encoder (or generally 2^(n-1)-to-n) -- not priority, but telling how many inputs are on?
This is not homework (not taking any classes) although it could be homework. I am wondering what is the easiest implementation using a single TTL chip or gates (fewest chip count) to encode the number ...
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How many logic gates does it take to implement base-100 addition?
I'm curious about the trade-offs that have been made in implementing different kinds of arithmetic in different models of computers, to which I'm trying to understand what the costs of various options ...
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12-bit pipelined adder
I have been given the task of designing a 12-bit pipelined adder:
There are 4-bit adders connected by latches.
Why are latches used between the 4-bit adders? Is it for synchronization?
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adder in binary addition: XOR instead of OR gate
I am just a newbie starting out in electronics with no experience.
Why do we need XOR and AND gate for the binary adder? is there any particular reason why only these two specific gates are needed ...
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Propagation delay in shift register - in the context of a serial adder
The first figure (from Fundamentals of Logic Design, Roth/Kinney, 6th Ed, p.404) shows a serial adder which feeds in operand bits and stores the sum, and uses a D flip-flop to store the carry-out from ...
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4 bit adder(SN74LS283N) not working properly
simulate this circuit – Schematic created using CircuitLab
Hey guys
I've been trying to use a 4bit adder IC, but there are 2 main problems I've found which prevent me from using it:
If power ...
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Half adder with soft latching input buttons
I'm trying to build a half adder with soft-latching buttons as input, using only transistors. I looked up online for some ideas and managed to build a soft-latching input circuit and a half adder ...
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How do I use a 4-bit Adder, 4-1 MUX, and 2-1 MUX to implement various micro-operations on registers?
One of the exercises in my Logic Design coursebook requires me to create a circuit that handles following micro-operations on 4-bit registers R1 and R2.
R1 + R2
R1 - R2
R2 – R1
R1 – 1
-(R1 + 1)
0
-1
...
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Shift left followed by round for performing: y=x+cz in hardware
I wan't to implement a simple arithmetic, given the following (say 8 bits) integers x,y,z
$$y = x + c z$$
where 'c' is a fraction of a power of 2: 2^-1, 2^-2, 2^-3,...
I was adviced to perform the ...
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Carry Look Ahead adder propagation delay calculation
I'm studying Digital Design and Computer Architecture book, I'm stuck in the section of the carry-lookahead adder because there's something that I don't fully ...
