Questions tagged [adder]
Digital circuits that adds values
202
questions
4
votes
3answers
443 views
What does “2 digit BCD number” mean?
When I read it, I think a 2 digit BCD number is something between 0 and 99 in decimal. So, for example, 0100 1001 is a 2 digit BCD number and decimal equivalent of it is 49 in my opinion.
However, ...
0
votes
2answers
38 views
0
votes
1answer
32 views
Toggle between Half-adder and Half-subtractor
I have constructed a half-adder that looks like this:
And a half-subtractor like this:
It's basically the same circuit except the AND gate at the bottom has a NOT ...
0
votes
0answers
34 views
Which topology is used in practice to couple a noise generator to a signal?
I want to add noise (from a noise generator hardware) to a sine wave signal. The sine wave signal is coming from a function generator. The noise is generated by another hardware.
What is the method ...
0
votes
2answers
35 views
Output not working on 74F283 Adder
I am using a 74F283PC 4 bit adder, and I am not sure why, but the LEDs are not working, like they will not change at all. I have no idea why it's not working, and I could use any help.
This is the ...
0
votes
1answer
47 views
3 Bit Adder Logic Circuit Design
Im trying to design a logic circuit for a 3 bit adder using 6 inputs, A2, A1, A0, B2, B1, B0 and 4 outputs, s0, s1, s2 and c (the carry out). I already have circuits for a half adder, full adder and a ...
0
votes
1answer
103 views
Displaying 6 bit numbers on two 7-segment displays
I designed 6 bit binary adder which should add two numbers in first complement. The numbers are being input via registers. I have to display the numbers and the result on two 7-segment displays via ...
1
vote
1answer
61 views
How do I implement the clock into this testbench?
I am trying to write a testbench for an adder/subtractor but when it compiles the clock does not shift.
Here is the verilog for the adder/subtractor:
...
0
votes
1answer
52 views
Amplifier Circuit as a Signal Adder
Consider two input signals, v1(t) and v2(t). Each has a source resistance of 10 kΩ. We require the output signal to be the weighted sum of the two inputs,
vo(t) = 15v1(t) + 20v2(t),
delivered to a ...
-1
votes
1answer
68 views
I want to implement an Adder for 8-bit signed numbers coded with 1’s Complement representation
I am having a hard time trying to implement an adder for 8-bits signed numbers with 1's complement but without using VHDL since I am new to this kind of stuff.
But I know that I should use 8 full ...
0
votes
0answers
29 views
Worst case scenerio in carry skip adder?
I am having trouble understanding this.
worst case operation time takes place when
carry is generated in the first block
carry skips intermediate stages
carry is killed in the last ...
0
votes
1answer
34 views
Design input of the 4 bit adder
I have the answer. But i'm not sure how the input of the adder is derived.
Why is it a,b,1,1 for x and 0,a,b,0 for y?
Been searching multiple sources but i'm stuck. Trying to study for my exams.
1
vote
1answer
62 views
Please help! Implement 4-bit Incrementer with two 74LS163 + 74LS74A + XNOR gate(s) + AND gate(s)
The Question
Use two 74LS163, one 74LS74A, XNOR gates and AND gate(s) to build a circit that can "add" two given "4-bit binary numbers" A and B.
Here is how the circuit computes SUM = A+B (for SUM &...
0
votes
0answers
81 views
VHDL - signed vs unsigned adder
I have made a four bit adder with carry-in & -out that contains an unsigned and signed architecture:
...
0
votes
0answers
43 views
What would happen if a negative voltage is given to an op amp adder circuit?
Would it subtract that voltage because it would reduce the total current going on the feedback resistor ?
1
vote
2answers
60 views
What is a Carry Propagate Adder?
It's in my syllabus but there's no mention of it in my book. Can someone explain to me what is a Carry Propagate Adder?
0
votes
1answer
65 views
Making a simple 4 bit adder into a 4 bit adder with carry in & out
I have coded a simple signed 4 bit adder. It doesn't have any carry in or carry out so it easily overflows.
Below you can see my code.
...
10
votes
3answers
3k views
How should I understand FPGA architecture? [closed]
I've been given the task to make a 2-bit adder by programming a FPGA. The FPGA is seen below:
However, I don't even know how to begin this task, because I don't understand what I am looking at.
...
0
votes
2answers
120 views
VHDL: difference between using “+” or writing our own adder
I would like to know what would be the difference between between using "+" or writing an adder for adding two numbers:
...
-1
votes
1answer
58 views
Different types of full adders
I programmed a full adder in VHDL as shown in the picture below:
However, when compiling it, I get the following diagram when I open the Technology Map Viewer:
My compilation report also says that I ...
0
votes
0answers
37 views
How to cascade multiple look ahead adders
I know how we can prepare 4 bit look-ahead carry adder (CLAs) to avoid delay involved in rippling of carries in ripple carry adder. We calculate various signal in CLA as follows:
Carry propagate ...
0
votes
1answer
53 views
Designing a Carry lookahead unit using EEPROMs, creates osclillator
I have read something about CLUs (Carry lookahead units) and want to build one. I have settled on design using eeproms as adders ...
0
votes
2answers
61 views
How does carry in work in full adders?
Yesterday I asked a similar question and realized I still don't quite get it, so I'm sorry about that.
Here is explicitly what I mean:
This is a part of a full adder. The first row in which ...
0
votes
4answers
218 views
binary addition / truth table?
I'm trying to understand how binary addition works.
If I understand it correctly, with two variables e.g. x and y you add a ...
0
votes
1answer
91 views
Efficiently calculate \$-x-y\$ using a single adder
I would like to know if there is an efficient way of implementing the operation \$-x-y\$ on an FPGA using only a single chain of adders or subtractors, roughly equal in length to the maximum number of ...
2
votes
3answers
150 views
How does a “standard” ripple carry adder behave?
I came across the following problem:
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is ...
2
votes
1answer
39 views
Relative difficulty between leading zero counting and addition
Consider a 32-bit or 64-bit ALU that must implement both count leading zeros and integer addition, with low latency (say a few cycles), implemented on a modern high frequency logic process.
Which is ...
1
vote
1answer
177 views
2's Complement 4 Bit adder. (Multisim)
I am hoping I am doing something dumb here. I know there are other posts about this but everything I have found leads me to believe my circuit should be working. Yes this is for homework. No, I am not ...
0
votes
0answers
27 views
ripple-borrow binary subtraction circuit
How does this patented ripple-borrow binary subtraction circuit eliminate the need for doing two-complement conversion on the input, thus saves on hardware circuit computation area and time ?
0
votes
2answers
122 views
simple six-position voting machine into a 7 position voting machine
I'm new to learning about full and half adders and what not. but I am struggling to understand this question out of my study manual.
The pictures shows a simple six-position voting machine module ...
-1
votes
1answer
47 views
What is the purpose of carry-in in full adder? If carry in equals carry out of previous adder, then I have question
In 5th row carry out is 0 then why is carry-in equal to 1 in next adder?
0
votes
0answers
36 views
Propagation delay in full adder models
From my last question Propgation delay
I tried to solve for the time delay that occurs at the last carry
Not sure if I have done it right .. Please correct me if I m wrong
-1
votes
1answer
127 views
FPGA too slow for my ripple carry adder?
I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
0
votes
1answer
157 views
0
votes
1answer
147 views
3 bit full adder designing
I am new to the concepts of using adders to add numbers but I tried using the definitions which I understood as given two binary digits A, B the full adder takes three inputs A, B, C where C acts as a ...
0
votes
2answers
109 views
Full Adder Circuit
This circuit is based around the SN74HC283 4 bit full adder.
What purpose does the resistor network serve?
Will this circuit work without any resistors, i.e. using raw inputs and outputs?
...
0
votes
2answers
92 views
Instantiating modules in SystemVerilog
This is a picture of a system that I am building:
(original)
I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
0
votes
1answer
1k views
Implementing a 4-bit ripple carry adder/subtractor using structural VHDL
I have to create a 4-bit ripple carry adder/subtractor. The circuit will have two 4-bit data inputs (A and B), a control line (Add/Sub), a 4-bit data outputs (S) and a carry out bit (Cout).
I have ...
0
votes
1answer
80 views
Parallel Prefix Adder explained
I think I have understood Carry Lookahead adders.
However, I don't really understand how parallel prefix adders evolve from carry lookaheads. Can someone explain to me the difference between PPA and ...
0
votes
1answer
601 views
Verilog counter made of 32 bit adder (syntax error)
For a school assignment I have to make a counter, based on a 32-bit adder, that increments with 1 every clockcycle if 'enable = high' and 'reset = low'.
When I try to use the adder in my counter ...
0
votes
1answer
163 views
problem with 6 bit adder
I am working on Subtractor circuits using Adder circuits. I have to do x-y.
Suppose x = 111111 , y = 100000
Using the 6 bit adder circuit I created the overflow flag is coming to be 0 but when I ...
0
votes
1answer
706 views
Converting full adder to subtractor using inverter
I've been trying to convert a full adder to a full subtractor using an inverter.
I tried using not gates at the B input ( in A B Cin ) and also using it in the outputs but the final answers are not ...
0
votes
0answers
248 views
Designing Excess 5 to BCD using Binary parallel adder
I've been trying to form a combinational logic circuit of converting excess 5 to BCD. I've been able to make a normal logic circuit but I do not know what a binary parallel adder is.
My attempt - ...
0
votes
1answer
400 views
4-Bit Adder Subtractor Quartus Prime Lite
I designed a 4-bit adder/subtractor circuit in Quartus Prime Lite. I am struggling with getting the correct output on the waveform. It is supposed to take the unsigned decimal numbers and add or ...
-1
votes
3answers
285 views
Why does a full adder need an OR gate?
I have read and I understand how the full adder works (or atleast I think I do :D). It combines two half adders and either one of them can have a carry over, hence the OR gate. But why do we need ...
0
votes
1answer
743 views
About the critical path of ripple adder
I have trouble understanding what's critical path delay of n-bit Ripple Carry Adder. In the book I read, given N-bit Ripple Carry Adder formed from N single 1-bit full adder:
the critical path ...
0
votes
1answer
188 views
Adding multiple differential signal
As I asked in "Adding multiple analog signal" before, I got that: for adding some signal together, we can only use op-amp, instead of lovely integrated circuit (ough).
But the question arise because ...
0
votes
2answers
167 views
Adding multiple analog signal
I'm trying to add 4 output of ADA8282 together and create only one analog signal with bandwidth about 6 MHz, I know Op-Amp adder as "How can I add three AC signals?" and "ElectronicTutorial" said. ...
0
votes
1answer
377 views
How do I make a double dabble circuit with logic gates
Im attempting to make a 8 bit binary calculator that displays on multiple seven segment displays. Can double dabble be done with logic gates. If so, how?
0
votes
2answers
33 views
Doubt about half adder timing
In my book there is the architecture of a basic circuit with a half adder with 1 AND and 1 XOR for the carry, and a "maimed" half adder with one XOR for the previous carry. Then book say that minimum ...
