Questions tagged [adder]
Digital circuits that adds values
248
questions
-2
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0answers
32 views
Find the lenght of the critical path of carry out and for the sum generation [closed]
I don't know what the problem wants in fact . I know that critical path is the longest path in the project schedule network diagram, and is the shortest possible duration for the project.Just tell me ...
-3
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0answers
49 views
Does anyone knows what a 8421 adder circuit and what its used for?
We are learning different types of logic gates then we come across an application of it which are full adder and half adder. After constructing it using logic gates we are tasked to construct an 8421 ...
1
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1answer
44 views
Is it mandatory to sign-extend when adding two different-sized buses?
I am trying to optimize a critical path in my design. The bottle-neck of the path is a 32-bit ADDER between a 32-bit bus and a sign-extended 16-bit bus. At first, when I didn't realize it was signed, ...
3
votes
1answer
659 views
I am unable to figure out how the answer to following question is 70ns
Here's the question:
Each full adder has 2 AND gates 2 XOR and 1 OR gate so carry propagation delay for each full adder should be 80 ns by the data provided and as there are 4 full adders, so shouldn'...
1
vote
1answer
81 views
Minimizing delay of Full Adder
It is said that by exploiting the inverting property we can "reduce one inverter delay in each full adder". Why is that?
Clearly, we can reduce one for the input of the first adder, but we ...
0
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0answers
22 views
Inversion property of full adder
The given inverting property states that the FA stays the same if I invert all the inputs and outputs.
Using this idea we modify the ripple carry adder into the below form, but why it can be ...
1
vote
1answer
47 views
Full adder Cout expression issue
The truth table of a full adder is as below.
Cout is given as Cout = AB + Cin(A XOR B).
not sure why is that because when I do my k-map on the Cout, I get Cout = AB + Cin(A+B).
does anyone know why is ...
1
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0answers
121 views
Carry-select adder - Time calculation
a) Suppose a binary pick-up adder (carry-select) of 32-bits, comprising 4 sub-sections adders spreading carry of range 8 bits. Show the values obtained internally in the circuit of this adder to ...
0
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1answer
127 views
Does a 64-bit computer require 64 full adders to perform additions/subtractions, or would it somehow require less?
I have seen online these diagrams for 4-bit adders which feature 4 individual full adders chained together with the carry out from the previous feeding into the carry in to the next.. Likewise, to add ...
0
votes
1answer
181 views
Building an 8-bit adder/subtractor using two 4-bit adder/subtractors and the result has a difference of 16 for values above 16
I'm trying to build an 8-bit adder/subtractor using two 4-bit adder/subtractors
The result is always 16 below the required value when adding two numbers above 16 and 16 above the required value when ...
0
votes
1answer
65 views
Bits are toggled in step 1 or 9's complement is done using subtraction?
In base 2, I want to subtract x-y using adder. Where, x = (1011)2 and y = (0101)2
[For verification, in decimal x=(11)10, y = (5)10. So, we are seeking (6)10 as the answer ]
In base 2 using adder we ...
1
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0answers
34 views
Carry Skip (Bypass) Adder wcs vs Crit. Path
I'm studying adder types and, as the title says, I'm having a problem with the carry-skip.
From what I know the critical path of an equal blocks carry-skip adder is supposed to go from the LSB of the ...
0
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2answers
143 views
0
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1answer
70 views
Additional bits computation in VHDL
Given an array of N elements, element is M bits vector. I am going to sum them up.
For example, given an array of 12 bits vectors.
...
1
vote
1answer
68 views
What is wrong with my 2 bit adder? [closed]
I'm trying to make a 2 bit adder in Logism. I made a half adder and a full adder chained together. Some equations work, and some don't. I'm using the structure that I see everywhere on how to make an ...
1
vote
1answer
119 views
How to capture output of adder?
I am experimenting with a circuit for adding two numbers represented by two digital counters and two cascaded 4 bits adders (74HC283). I tested separately with cascaded 74HC163 and with asynchronous ...
0
votes
0answers
287 views
8-bit BINARY for (3) 7-segment display using Shift and Add-3 Method
We have been told by our professor to create an 8-bit Adder-Subtractor and will display an output in decimal instead of just using LED's in Multisim. We know that in order to do this, we need to ...
0
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0answers
64 views
Arithmetic - Absolute value
I constructed a circuit that calculates the absolute value of a signed 4-bit number in two's complement
Then the second question of the exercise was to show the correctness of my circuit using the ...
0
votes
2answers
168 views
Transistor full adder circuit [duplicate]
I'm building a full adder circuit using transistors. I am only doing it for fun, that's why I'm not using IC gates.
I am feeding it 5V and I'm getting really strange outputs. And it isn't even ...
0
votes
2answers
74 views
How do I create a 1-bit full adder that outputs a 2-bit sum?
I am trying to build a 1-bit full adder that outputs a 2-bit sum.
I know that the standard 1-bit FA outputs a 1-bit sum and a carry bit, but I was wondering how can I modify the FA such that the carry ...
3
votes
2answers
109 views
How to reason about this 'adder with memory' circuit?
I'm reading through "Code" by Charles Petzold and I had a question about the following circuit illustrated in the book:
Let's assume that the latches in the 16-bit counter and the 8-bit ...
1
vote
1answer
81 views
Time (Propagation delay) taken for adding 3 n-bit binary numbers using Carry Propagate Adders (Ripple carry adders)
While being introduced to carry save addition technique, I was told that the time taken for adding 3 n-bit binary numbers using ripple carry adders will be (2n+1)t_FA (Assuming we neglect the minor ...
0
votes
1answer
429 views
Designing lookup table(LUT) for half adder in FPGA
I want to implement half adder using FPGA. For this I need to design CLB, more specifically LUT for half adder. I know LUT gives only one output. But, for half adder we get two output. One for sum and ...
1
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0answers
45 views
Building a better staged 1's complement adder tree?
I'm trying to calculate the checksum of IPv4 and UDP messages coming out of my Ethernet controller module. The checksum calculation for both IPv4 and UDP is defined as 1's complement addition, which ...
1
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0answers
182 views
Convert from 4 bit binary number to 2 bit binary number
I am currently using logisim to output a 2 bit binary number, however, the bit adder releases 4 bit binary number instead. Is there any way to fix this? (I am currently using v 2.14.6 .)
1
vote
2answers
717 views
Given 4 inputs (A,B,C,D) how can I design a circuit that counts the number of 1s?
The question is in the title.
If I have 4 inputs, how can I count the number of 1s using full/half adders and produce the binary equivalent of how many 1s exist in the 4 inputs?
2
votes
0answers
80 views
Full adder 2D addressing
I try to implement a full adder circuit using square arrays.
I've used Digital software to design it. Also I've tested it. It works fine.
But my implementation is quite different from the circuit ...
0
votes
3answers
158 views
Overflow in Adder Circuits
We were learning about full adder and half adder circuits and how overflow might occur in them. My professor told that for a full adder of n bits the range is [-2^(n-1) , 2^(n-1)-1]. What I don't get ...
2
votes
3answers
348 views
Simplify the boolean function $$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$
I want to simplify the following boolean function:
$$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$
Here's my attempt:
\begin{align}
Z &= A\bar B \bar{C_i} + \bar A B ...
3
votes
1answer
157 views
What parts/sections of a CPU take the biggest number of transistors?
I was surprised to hear CPUs only have a number of ALUs. What are most of the transistors in a CPU dedicated to?
1
vote
1answer
107 views
How can I generate overflow condition from a 74'283 or 74'181 adder without an output pin of the carry-in of the MSB?
I've been building my own CPU from low level chips, using the 74LS283 adder. And I've been wondering about how to set the overflow flag. Finally I seem to have grasped that the overflow flag is the ...
1
vote
1answer
91 views
3-to-2 line encoder (or generally 2^(n-1)-to-n) -- not priority, but telling how many inputs are on?
This is not homework (not taking any classes) although it could be homework. I am wondering what is the easiest implementation using a single TTL chip or gates (fewest chip count) to encode the number ...
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votes
3answers
640 views
0
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0answers
42 views
How many logic gates does it take to implement base-100 addition?
I'm curious about the trade-offs that have been made in implementing different kinds of arithmetic in different models of computers, to which I'm trying to understand what the costs of various options ...
0
votes
2answers
170 views
12-bit pipelined adder
I have been given the task of designing a 12-bit pipelined adder:
There are 4-bit adders connected by latches.
Why are latches used between the 4-bit adders? Is it for synchronization?
1
vote
2answers
160 views
adder in binary addition: XOR instead of OR gate
I am just a newbie starting out in electronics with no experience.
Why do we need XOR and AND gate for the binary adder? is there any particular reason why only these two specific gates are needed ...
1
vote
1answer
187 views
Propagation delay in shift register - in the context of a serial adder
The first figure (from Fundamentals of Logic Design, Roth/Kinney, 6th Ed, p.404) shows a serial adder which feeds in operand bits and stores the sum, and uses a D flip-flop to store the carry-out from ...
1
vote
1answer
104 views
4 bit adder(SN74LS283N) not working properly
simulate this circuit – Schematic created using CircuitLab
Hey guys
I've been trying to use a 4bit adder IC, but there are 2 main problems I've found which prevent me from using it:
If power ...
0
votes
0answers
41 views
Half adder with soft latching input buttons
I'm trying to build a half adder with soft-latching buttons as input, using only transistors. I looked up online for some ideas and managed to build a soft-latching input circuit and a half adder ...
0
votes
1answer
339 views
How do I use a 4-bit Adder, 4-1 MUX, and 2-1 MUX to implement various micro-operations on registers?
One of the exercises in my Logic Design coursebook requires me to create a circuit that handles following micro-operations on 4-bit registers R1 and R2.
R1 + R2
R1 - R2
R2 – R1
R1 – 1
-(R1 + 1)
0
-1
...
0
votes
2answers
33 views
Shift left followed by round for performing: y=x+cz in hardware
I wan't to implement a simple arithmetic, given the following (say 8 bits) integers x,y,z
$$y = x + c z$$
where 'c' is a fraction of a power of 2: 2^-1, 2^-2, 2^-3,...
I was adviced to perform the ...
3
votes
2answers
3k views
Carry Look Ahead adder propagation delay calculation
I'm studying Digital Design and Computer Architecture book, I'm stuck in the section of the carry-lookahead adder because there's something that I don't fully ...
0
votes
1answer
33 views
Implementing a total sum with logic gates
I'm trying to implement a total sum that looks like this.
TOTAL = TOTAL + INPUT
I'm using binary adders to add and D flip flops to store TOTAL. However, whenever ...
0
votes
1answer
69 views
Preset D flip flop as 0 for total sum
I'm trying to implement a total sum that follows this code
SUM = SUM + INPUT
SUM and INPUT are 5 bit signals in binary. I know how to implement the adder and i ...
0
votes
0answers
46 views
Is it possible to speculate on the completion of an adder from the first row?
I've seen speculative adders that take an extra clock cycle something on the order of once in 10^5 additions. Often papers on speculative adders claim to need the information from stage 1 and stage <...
1
vote
2answers
442 views
Why is the last carry block's gate in a full adder an OR gate (and not a XOR)?
It seems that a half adder (there are 2 inside a full adder) can't output both HIGH values for sum and carry, it's either Sum is 1 and Carry is 0 or the inverse. It's never Sum = 1 and Carry = 1.
To ...
5
votes
3answers
2k views
What does "2 digit BCD number" mean?
When I read it, I think a \$2\$-digit BCD number is something between \$0\$ and \$99\$ in decimal. So, for example, \$0100 1001\$ is a \$2\$-digit BCD number and decimal equivalent of it is \$49\$ in ...
0
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2answers
140 views
0
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1answer
47 views
Toggle between Half-adder and Half-subtractor
I have constructed a half-adder that looks like this:
And a half-subtractor like this:
It's basically the same circuit except the AND gate at the bottom has a NOT ...
0
votes
0answers
44 views
Which topology is used in practice to couple a noise generator to a signal?
I want to add noise (from a noise generator hardware) to a sine wave signal. The sine wave signal is coming from a function generator. The noise is generated by another hardware.
What is the method ...
