Questions tagged [adder]

Digital circuits that adds values

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10
votes
3answers
3k views

How should I understand FPGA architecture? [on hold]

I've been given the task to make a 2-bit adder by programming a FPGA. The FPGA is seen below: However, I don't even know how to begin this task, because I don't understand what I am looking at. ...
0
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2answers
106 views

VHDL: difference between using “+” or writing our own adder

I would like to know what would be the difference between between using "+" or writing an adder for adding two numbers: ...
0
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1answer
2k views

Time complexity of carry look ahead adder

How is the time complexity of carry look ahead adder O(log n)? Can you explain in terms of gate delays?
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1answer
384 views

Some questions about Carry-lookahead adder and Ripple-Carry Adder

I was reading about the Carry-lookahead adder and about the Ripple-Carry Adder. I saw some designs and it made me wonder the following questions: Both questions are the same for both adders so i'll ...
0
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1answer
850 views

Bcd subtractor units connections

I'm new in electronics. I'm trying to make a BCD calculator, but I got stuck in BCD subtraction. I got stuck in: how can I connect multiple bcd subtrator units? I'm trying to make a 3 digit calculator,...
7
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3answers
7k views

Critical path for Carry-Skip adder

Can anybody explain why Carry-Skip adder has the same critical path as regular Carry-Ripple adder. My textbook says that critical path occurs when carry is generated in LSB and then propagating it ...
-1
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1answer
53 views

Different types of full adders

I programmed a full adder in VHDL as shown in the picture below: However, when compiling it, I get the following diagram when I open the Technology Map Viewer: My compilation report also says that I ...
0
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1answer
457 views

best and worst-case delay of an adder

I have designed a 32-bit adder using a hierarchical carry look-ahead design. I'm now trying to run a spice simulation of this adder and am wondering what inputs will provide the best and worst-case ...
0
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0answers
23 views

How to cascade multiple look ahead adders

I know how we can prepare 4 bit look-ahead carry adder (CLAs) to avoid delay involved in rippling of carries in ripple carry adder. We calculate various signal in CLA as follows: Carry propagate ...
1
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2answers
305 views

Integrating an AND gate into another logic gate

I am attempting to make a 4 bit computer with transistors. I've made a half-adder without too much trouble, but now I'm trying to incorporate the AND gate's output (the carry) into the next adder. ...
0
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1answer
44 views

Designing a Carry lookahead unit using EEPROMs, creates osclillator

I have read something about CLUs (Carry lookahead units) and want to build one. I have settled on design using eeproms as adders ...
0
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1answer
682 views

using generate statement in verilog

I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
0
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2answers
58 views

How does carry in work in full adders?

Yesterday I asked a similar question and realized I still don't quite get it, so I'm sorry about that. Here is explicitly what I mean: This is a part of a full adder. The first row in which ...
0
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4answers
71 views

binary addition / truth table?

I'm trying to understand how binary addition works. If I understand it correctly, with two variables e.g. x and y you add a ...
0
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1answer
251 views

4-Bit Adder Subtractor Quartus Prime Lite

I designed a 4-bit adder/subtractor circuit in Quartus Prime Lite. I am struggling with getting the correct output on the waveform. It is supposed to take the unsigned decimal numbers and add or ...
0
votes
1answer
253 views

creating a circuit using half/full adder

My brother got this at school I cant help him with, I am thankfull for any help/advices On a street there are 2 traffic lights - one for people and one for cars. Both traffic lights have a button ...
0
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1answer
501 views

Implementing a 4-bit ripple carry adder/subtractor using structural VHDL

I have to create a 4-bit ripple carry adder/subtractor. The circuit will have two 4-bit data inputs (A and B), a control line (Add/Sub), a 4-bit data outputs (S) and a carry out bit (Cout). I have ...
0
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1answer
89 views

Efficiently calculate \$-x-y\$ using a single adder

I would like to know if there is an efficient way of implementing the operation \$-x-y\$ on an FPGA using only a single chain of adders or subtractors, roughly equal in length to the maximum number of ...
2
votes
3answers
96 views

How does a “standard” ripple carry adder behave?

I came across the following problem: A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is ...
1
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1answer
32 views

Relative difficulty between leading zero counting and addition

Consider a 32-bit or 64-bit ALU that must implement both count leading zeros and integer addition, with low latency (say a few cycles), implemented on a modern high frequency logic process. Which is ...
1
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1answer
71 views

2's Complement 4 Bit adder. (Multisim)

I am hoping I am doing something dumb here. I know there are other posts about this but everything I have found leads me to believe my circuit should be working. Yes this is for homework. No, I am not ...
0
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1answer
430 views

About the critical path of ripple adder

I have trouble understanding what's critical path delay of n-bit Ripple Carry Adder. In the book I read, given N-bit Ripple Carry Adder formed from N single 1-bit full adder: the critical path ...
0
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0answers
25 views

ripple-borrow binary subtraction circuit

How does this patented ripple-borrow binary subtraction circuit eliminate the need for doing two-complement conversion on the input, thus saves on hardware circuit computation area and time ?
0
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2answers
67 views

simple six-position voting machine into a 7 position voting machine

I'm new to learning about full and half adders and what not. but I am struggling to understand this question out of my study manual. The pictures shows a simple six-position voting machine module ...
-1
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1answer
40 views
1
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1answer
2k views

Propagation delay in full adder

I'm dealing with a question about an implementation of a full adder with component delays. tpd(XOR) = 5 ns tpd(AND) = 2 ns tpd(OR) = 2 ns I'm having problems solving for the the propagation delay ...
0
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0answers
27 views

Propagation delay in full adder models

From my last question Propgation delay I tried to solve for the time delay that occurs at the last carry Not sure if I have done it right .. Please correct me if I m wrong
0
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0answers
79 views

VHDL - How to add several numbers parallel

i would like to add several (variable number N, fixed size) numbers in VHDL. In the image below you see how i want to do the additions. In this example there are N=6 numbers (A0 - A5). I have a ...
-1
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1answer
113 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
0
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1answer
76 views

Full Adder driven by clock [FPGA/VHDL]

I've got Ripple Carry adder (26bit) made from scratch. ...
0
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1answer
57 views

3 bit full adder designing

I am new to the concepts of using adders to add numbers but I tried using the definitions which I understood as given two binary digits A, B the full adder takes three inputs A, B, C where C acts as a ...
0
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2answers
74 views

Full Adder Circuit

This circuit is based around the SN74HC283 4 bit full adder. What purpose does the resistor network serve? Will this circuit work without any resistors, i.e. using raw inputs and outputs? ...
0
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2answers
46 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
0
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1answer
40 views

Parallel Prefix Adder explained

I think I have understood Carry Lookahead adders. However, I don't really understand how parallel prefix adders evolve from carry lookaheads. Can someone explain to me the difference between PPA and ...
0
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1answer
198 views

Verilog counter made of 32 bit adder (syntax error)

For a school assignment I have to make a counter, based on a 32-bit adder, that increments with 1 every clockcycle if 'enable = high' and 'reset = low'. When I try to use the adder in my counter ...
0
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1answer
105 views

problem with 6 bit adder

I am working on Subtractor circuits using Adder circuits. I have to do x-y. Suppose x = 111111 , y = 100000 Using the 6 bit adder circuit I created the overflow flag is coming to be 0 but when I ...
0
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1answer
415 views

Converting full adder to subtractor using inverter

I've been trying to convert a full adder to a full subtractor using an inverter. I tried using not gates at the B input ( in A B Cin ) and also using it in the outputs but the final answers are not ...
0
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1answer
449 views

Can we form any circuit using half adders only? (assuming we have as many half adders as we want)

Using various combinations on half adders I get these outputs: {0,1,1,0},{0,0,0,1},{0,0,0,0},{0,1,1,1} And I also know that we can form any gets using NAND ...
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0answers
146 views

Designing Excess 5 to BCD using Binary parallel adder

I've been trying to form a combinational logic circuit of converting excess 5 to BCD. I've been able to make a normal logic circuit but I do not know what a binary parallel adder is. My attempt - ...
1
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2answers
11k views

How to make 2 bit or more half adder circuit

I have no idea about electronics, this semester school gave us a strange and confusing lecture about circuits which we shouldn't take because we are no engineer or something close. Question is we ...
1
vote
1answer
31k views

Design a full adder of two 1-bit numbers using multiplexers 4/1

How can i implement the full adder of two 1-bit numbers using only multiplexers 4/1? I created a truth table for a one-bit full adder, which looks like this: A = first bit B = second bit Pu = bit ...
0
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1answer
131 views

Adding multiple differential signal

As I asked in "Adding multiple analog signal" before, I got that: for adding some signal together, we can only use op-amp, instead of lovely integrated circuit (ough). But the question arise because ...
-1
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3answers
159 views

Why does a full adder need an OR gate?

I have read and I understand how the full adder works (or atleast I think I do :D). It combines two half adders and either one of them can have a carry over, hence the OR gate. But why do we need ...
0
votes
2answers
107 views

Adding multiple analog signal

I'm trying to add 4 output of ADA8282 together and create only one analog signal with bandwidth about 6 MHz, I know Op-Amp adder as "How can I add three AC signals?" and "ElectronicTutorial" said. ...
0
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1answer
265 views

How do I make a double dabble circuit with logic gates

Im attempting to make a 8 bit binary calculator that displays on multiple seven segment displays. Can double dabble be done with logic gates. If so, how?
0
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2answers
33 views

Doubt about half adder timing

In my book there is the architecture of a basic circuit with a half adder with 1 AND and 1 XOR for the carry, and a "maimed" half adder with one XOR for the previous carry. Then book say that minimum ...
-2
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1answer
2k views

Difference between Full Adder, Parallel Adder and Ripple Carry Adder?

I am a student and i cannot find any prominent difference between the full adder, parallel adder and ripple carry adder. The full adder for n-bit number requires n full adder cascaded, so as the ...
1
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0answers
57 views

How do I draw the truth table of an adder/subtractor that sets flags, and those flags are the inputs of a comparator?

How do I draw a truth table of a circuit that : starts off with a full adder/subtractor outputs the result F based on the two inputs (add if opcode is 0, subtract if opcode is 1) then output three ...
0
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2answers
181 views

Compare two numbers of four bits

I have two numbers both with four bits (a3 to a0 and b3 to b0 reading from left to right) and I would like to find out if a is bigger than b. I have drawn a solution of mine and a short mathematical ...
0
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1answer
409 views

Ripple carry adder doubt

In a 4 bit ripple carry adder 4 full adders are connected serially, one FA waits for the carry input from the previous FA. My question is, when calculating the propagation delay, should we assume that ...