Questions tagged [adder]

Digital circuits that adds values

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14
votes
1answer
593 views

Parallel prefix adder cells in Negabinary

I'm trying to design a parallel prefix adder for a negabinary based adder. Negabinary is base \$-2\$ instead of the familiar base \$2\$ binary. Each 1 bit adder generates a sum and two (instead of one ...
10
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3answers
2k views

How should I understand FPGA architecture?

I've been given the task to make a 2-bit adder by programming a FPGA. The FPGA is seen below: However, I don't even know how to begin this task, because I don't understand what I am looking at. ...
8
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3answers
3k views

Designing a simple ALU

I need to design an ALU with two 8-bit inputs A and B and control inputs x, y, and z that supports the following operations: ...
7
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3answers
2k views

check if an unsigned binary number is divisible by 15

I'm a computer science student and I got stuck on this question for hours. We have a binary unsigned number X, represented by 12 bits. We would like to build a system with 1 bit output - Y, that will ...
7
votes
3answers
7k views

Critical path for Carry-Skip adder

Can anybody explain why Carry-Skip adder has the same critical path as regular Carry-Ripple adder. My textbook says that critical path occurs when carry is generated in LSB and then propagating it ...
7
votes
1answer
28k views

What are carry-lookahead adders and ripple-carry adders?

I see carry-lookahead adders and ripple-carry adders terms being used often. I have no idea what either means (nor the type of architecture they describe). Can someone please explain what each one is,...
6
votes
3answers
932 views

What is the minimum amount of 1bit Full Adders required to implement the equation 4X + 3Y + 13?

Using 1bit FAs and 0/1 constants only, while X(x1,x2,x3) and ...
5
votes
1answer
22k views

How to determine overflow from an adder/subtractor?

I suppose in binary addition (no negative numbers), overflow happens when theres a carry out? Then for subtractor (2s complement), how do I determine it? From my understanding of my lecture notes, ...
4
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3answers
5k views

What is the purpose of a “carry in”?

I'm currently trying to learn how binary adders work, but I don't understand what a "carry in" is for. What is the purpose of a "carry in"?
4
votes
2answers
496 views

How to design system for n bits?

Say I want to design an n-bit system e.g. 256 bits. Can I generalize a 4-bit ALU which I think I know to 256 bits? These are my diagrams.
4
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4answers
5k views

Test Cases for 16-bit Ripple Carry Adder

I'm working on a lab for a course I have on VHDL, and part of it is to implement an n-bit ripple carry adder and then test it as a 16 bit adder. My problem is that I don't really know HOW to test it, ...
4
votes
1answer
2k views

What is wrong with my 2-bit adder?

I attempted to build an 8-bit adder in Logisim by carefully chaining together a half-adder and 7 full adders, all made from basic logic gates. Unfortunately, it produced erroneous results; for example,...
4
votes
2answers
4k views

How to determine if a Carry Look Ahead Adder Overflows

I am implementing a 32 bit CLA Adder like how a 16 bit adder is implemented in Wikipedia Problem is how do I determine if the block overflows? I will need the carry into bit 32 (which is now in the ...
4
votes
1answer
783 views

Building a small 4-bit adder on a breadboard

I am very new to using IC and basically a breadboard in general, but I am doing a project on how computers add and thought it would be nice to have a practical demonstration. My main question is, for ...
3
votes
2answers
4k views

Building a full adder with NPN BJT transistors

So I'm trying to wire up a full adder just with NPN BJT transistors (I know there is a 74XX283 4-bit binary full adder, but I want to do it just with transistors if possible for my own learning). The ...
3
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2answers
37k views

Binary Adder and Parallel Adder

Are binary adder and parallel adder same thing? I couldn't find any information about parellel adder in my book. Does anybody have an idea?
3
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6answers
905 views

Batteries in parallel vs voltage signals in parallel

From a practical point of view, when you connect two audio signals to one speaker the result is that both audio signals can be heard. That means the two voltage waves were added, correct? However, ...
3
votes
2answers
606 views

Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?

At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool. Out of curiosity, I hand-coded in Verilog ...
3
votes
1answer
9k views

Determining the truth table and simplifying logic expressions (full adder)

I've been taking an intro computer architecture class and doing some research of my own, I've found the following exercise: Determine the truth table and simplify the logic expression derived from the ...
3
votes
1answer
394 views

Half Adder and Two Function, A Contest Questions?

I ran into a 2013 contest question on computer-science filed. What is the following True about F and G function. (The output ...
3
votes
1answer
711 views

Carry-lookahead adder - what happens to carry bit?

I recreated and trying to understand for the sake of fun and learning the circuit that can be seen here on second page: Link . This is basically a 4-bit carry-lookahead adder, but there is one thing ...
3
votes
1answer
918 views

What is the critical path in the design?

I am trying to understand the worst case path in the 16bit carry bypass adder. Isn't the critical path through all the adders in the design? But the solution is shown as below, how can it be the ...
3
votes
1answer
865 views

adding two 64-bits number with m-bit carry ripple adder and multiplexer, a questions?

I ran into a question from computer architecture class. The professor says that for adding two 64-bit numbers A and B we use m-bit carry ripple adders and multiplexers such as following: and that for ...
3
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0answers
346 views

Floating point addition. Are guard, round and sticky bit always necessaryl? analysis of a special case

I've a particular case of floating point addition. As you know for given floating point numbers \$x,y\$ one of the steps of the addition involves the fixed point sum: $$ s = 1.m_x + (-1)^{s_x \oplus ...
2
votes
2answers
3k views

How can I add three AC signals?

I have three light sensors which outputs appropriate AC currents with respect to light intensities. I only have one pin left for my ADC IC that I have on my board so I can't sample three sensors using ...
2
votes
3answers
96 views

How does a “standard” ripple carry adder behave?

I came across the following problem: A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is ...
2
votes
1answer
6k views

How does this carry look ahead block work?

This is a carry look ahead adder : This adder is known to calculate one or more carry bits before the sum. From the figure we see that carry look ahead block calculates the carry C1,C2,C3,C4 . But i ...
2
votes
1answer
254 views

How does a half adder made of crossbar latches operate?

I am researching memristors, and one application that's frequently cited is a crossbar latch that sandwiches memristors between two layers of wires to form a grid. In most examples, this is configured ...
2
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2answers
466 views

Muxes, Adders, Comparators, and Gates

This question is actually from one of my previous discussions, which I still don't understand how to implement. The goal is to use abstraction to design a circuit, which converts two-digit ASCII ...
2
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1answer
5k views

How to find gate delay for 4-bit look-ahead carry adder?

How can I find Gate Delay for bit 1 of the sum by a 4-bit look-ahead carry adder?
2
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1answer
3k views

Can anyone explain to me how a carry select adder works?

Doesn't get more complex then the question above. I've been looking through textbooks and using google and I feel like the explanations are not suffice or unclear. Can anyone explain this to me well?
2
votes
1answer
254 views

Synchronizing multiplier with adder to form mac

I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the ...
2
votes
1answer
7k views

How do carry save adders work?

I thought I understood the concept but wikipedia has confused me. There are two outputs because one's for a partial sum and one's the carry bits. But why must it be used to "compute the sum of three ...
2
votes
1answer
32k views

How to calculate Gate Delays in normal Adders and Carry Look Ahead Adders

In my textbook the gate delays for the n-bit ripple adder is given as \$ 2n \$ for \$c_n\$ bits and \$ 2n-1 \$ for \$ s_n-1 \$ for the circuit as shown below: But, for a 4-bit Carry Look Ahead Adder ...
2
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2answers
273 views

Ultra low power adders and multiplier

I am working on a low frequency 30 khz module that needs to have an ultra low power consumption. The problem is the research focuses on improving the performance of the adders and multiplier and doesn'...
2
votes
2answers
1k views

How does one use both half and full adders together?

I am trying to teach myself the concept of (half and full) adders from Wikipedia and am a bit confused. Do I need to use both half adders and full adders together for performing multi-bit addition? ...
2
votes
1answer
1k views

Display Double Digit Numbers on 2 seven segment displays

I'm making an Arithmetic Logic Unit(ALU) for an assignment and I'm on a point. So according to my circuit design on the link shared below, I am able to output 1 digit of my alu. It is a 4 bit ALU so ...
2
votes
1answer
7k views

Serial Adder vhdl design

I've a design problem in VHDL with a serial adder. The block diagram is taken from a book. Since i'm not skilled enough in design with clock (except some silly flip flop i've found on the web, and ...
2
votes
1answer
283 views

Multioperand pipelined adder

in order to explain how to a pipelined multioperand adder could be implemented my book shows the image reported below. The idea is to use three adder with 4 stage pipeline. However i tried to make a ...
2
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0answers
134 views

Ling adder vs classic CLA adder what's the difference?

I'm practicing in designing vhdl unit with some "complex" computer arithmetic algorithm. I've just implemented the following CLA unit below. I'm reading through this book, page section 6.3 page 97, I ...
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0answers
1k views

How to compare carry-lookahead and ripple-carry adders?

I am a bit stuck with the concept of carry-lookahead adder so I'd like to compare it with another concept I'm more familiar with: the ripple-carry adder. I'm trying to make some basic math comparison ...
2
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1answer
3k views

Carry look ahead adder/subtractor & Overflow, Negative Bits

I am suppose to design a carry look ahead adder with ... Input flag bits E (Enable) S (Subtraction) Output The usual sum & carry out O (Overflow) N (Negative) Z (Zero) But the question is ...
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2answers
717 views

VHDL - Cheapest-Fastest unsigned to signed binary number converter

We know that to convert unsigned to signed (precisely, I want to convert a pure binary into CA2 number) we must negate the unsigned number adding, then, + 1. In VHDL I can implement an inverter and an ...
1
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1answer
7k views

Why is a half adder implemented with XOR gates instead of OR gates?

Half adder circuits are implemented with XOR gates for the summing. Why can't the adding function be implemented with OR gates? What is the difference between using XOR gates and OR gates?
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2answers
4k views

Which 4-bit Binary Number Is Greater?

My Task I'm working on an extra work question our teacher assigned us from the book. Design a combinatorial circuit that compares two 4-bit unsigned numbers A and B to see whether B is greater than A....
1
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1answer
873 views

calculate clock cycle of ripple Carry and lookahead adder

How would you find the number of clock cycles it takes to produce sum, the carry out, and overflow flag using ripple carry or lookahead adder. Can someone please explain me how would we go on finding ...
1
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2answers
2k views

8 bit octal full adder help

I have this project listen below and im not sure where to start maybe someone can give me a few pointers or perhaps point me in the right direction of starting this? Thanks!! Input: A, B = octal ...
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2answers
390 views

Question about 4-bit binary adder on 7 segment display and subtraction

In my lab, we successfully built a 4-bit binary parallel adder and were able to display the results of some tests on the 7 segment display. But our TA asked us to try something: subtract 1-9, and we ...
1
vote
1answer
7k views

How to multiply using gates?

I need to multiply 2 3bit numbers. I tried that: but it does not seem to work. In this example, the output should be 49. so that is that 77?
1
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1answer
32 views

Relative difficulty between leading zero counting and addition

Consider a 32-bit or 64-bit ALU that must implement both count leading zeros and integer addition, with low latency (say a few cycles), implemented on a modern high frequency logic process. Which is ...