Questions tagged [addressing]
The addressing tag has no usage guidance.
101
questions
4
votes
1answer
124 views
Microprocessor architecture bits vs bus sizes
I am ready following on this website:
"Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
0
votes
1answer
43 views
Address decoding different bank sizes in 64K memory
I'm doing a small Motorola 6809-based computer project, and since I'm a bit rusty when it comes to boolean algebra I'm wondering if I'm doing my address decoding a bit too complicated for my simple ...
0
votes
2answers
77 views
Addressing 45 Inputs Down to 6 pin Output
I'm looking for a chip which could minimize ~45 button inputs down to an 6 pin input for use with Raspberry Pi.
I know this is a simple problem and it has likely been solved before, but as an ...
1
vote
1answer
72 views
How many external devices can be linked to a CPU with n address buses and m data buses?
(Hypothetical)
Let's say there is a CPU with 8 address lines and 8 data lines.
If each external device has 128 accessible registers, how many external devices can be linked?
For 8 address lines, I ...
0
votes
1answer
98 views
Finding address space
Could somebody please explain how to find the address space for the RAM, Sensors, Alarm and ROM? :)
The answer is supposed to be
ROM: 0000-1FFF
RAM: 2000-3FFF
Sensors: FFF0 - FFFF
Alarm: FFFE
0
votes
2answers
219 views
Does pin A15 on a Z80 tell if the CPU is addressing ROM or RAM?
I am designing a simple, hobbyist single board computer similar to an Arduino using a Z80 CPU. The trouble I am running into is how the CPU addresses memory. I know that the Z80 uses pins A0-A15 to ...
1
vote
4answers
381 views
advantages of PC-relative addressing
I have read somewhere:
"The advantage of using
relative mode over direct mode is that relative addressing is a code which is position-independent, i.e. it can
be loaded anywhere in memory without ...
1
vote
2answers
50 views
Address bus, databus: how much storage direct accessible
I have a CPU with a 32 bits data bus and a 21 bits address bus. I would like to know how much storage I can connect to this CPU directly.
Does this depend on the address bus width, because I can ...
7
votes
3answers
455 views
Why are the SRAM data and address pins numbered? [duplicate]
As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins.
E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788....
1
vote
1answer
69 views
Would a parallel EEPROM ever output a value that it does not contain?
I understand that when the address input to a parallel EEPROM changes from A to B, the output may show results that aren't the contents of either A or B, for a few nanoseconds.
Are these spurious ...
0
votes
1answer
72 views
inverting address decoder with low after high
I have an 74137 address decoder and know how to build one like that from basic gates. But in my use case the address decoder is connected to the enable pins of a number of bus drivers and I fear this ...
0
votes
2answers
227 views
I2C Addressing after device address is known
I have an I2C device that I know the address is 0x70 (probed when connected to Raspberry Pi using i2cdetect -y 1). My issue is that the bytes I want to look at need to be called in WiringPi. The ...
0
votes
1answer
220 views
Cascaded i2c address translators?
I am trying to connect many (~80) ToF distance sensors VL53L0X onto a single i2c bus. They have the default i2c address 0x52, which is programmable, but not persistent. Thus I have a choice between ...
2
votes
1answer
482 views
Understanding GDDR5 clamshell mode
Let suppose a 256 bit memory controller is installed on a PCB with GDDR5 memory modules.
In normal mode you can split the lines into 8 group of 32 bit and drive 8 modules x 1Gbit (128 MB) = 1 GB of ...
-5
votes
1answer
269 views
Design logic circuit to address 2 x 512 kB RAM and 2x1024 MB RAM with 36 address lines? [closed]
How do you address 2 x 512 kB RAM and 2 x 1024 MB RAM with 40 address lines?
Memory is byte addressable, problem is to find out enough address lines to address all 4RAM and designing appropriate ...
0
votes
2answers
141 views
AT28C16 Interface Help
I pulled an AT28C16 from an old KVM switch and have managed to wire it up like so:
A0-10 -> GND
CE -> GND
WE -> 5V
OE -> GND
VCC -> 5V
GND -> GND
I/O0-7 -> Floating. Plugged by hand to level meter ...
-1
votes
1answer
99 views
Controlling motors same as WS2812b works (Neopixels)
Im a beginner and trying to achieve a weird scenario (Could be). There is around 30 tiny DC motors for each of those I need to make it individually controllable. Same as WS2812b led works. How can I ...
0
votes
1answer
193 views
What is slave select signal on the APB bus for?
I am currently working on an APB BFM and I have a question regarding the bus protocol. I understand every slave on APB bus has its own unique address space, where its internal registers are mapped. ...
0
votes
1answer
214 views
I2c slave address confusion?
Can someone explain which address will be used for ADV7511 for I2C if it is stated that it is either 0x72 or 0x7a in adv 7511programming guide [page 16]?
If I am right, we send 8 bits per transfer, ...
1
vote
1answer
54 views
Relate Bin file (read from uC) to map file
We have a AT32UC3C1512 presenting a Failure, part of the analysis that is normally performed to isolate the failure is to perform ABA swap of components, we have performed the swap in several ...
2
votes
2answers
175 views
what is an “Adressable” I2c device, and what does it mean?
The MCP3021 is a standard 10-bit ADC with an I2C Interface. It's datasheet can be found here.
In the general description, it says:
The
device is also addressable, allowing up to eight devices
...
0
votes
1answer
1k views
PCI device address actually means slot address? And when does PCIe slot get its' address?
I'd like to clarify how the configuration address space in PCI and PCIe works.
Namely, a PCI peripheral on a bus is addressed with device:function pair (the ...
1
vote
2answers
1k views
Arm mode and Thumb mode makes the PC's bit 0
The ARM and Thumb modes are word-aligned and halfword-aligned. I understand this means that if it's in ARM mode, the start of addresses must be divisible by 32, and if it's in Thumb mode it has to be ...
0
votes
1answer
43 views
Measure resistance (make connection) between array of points
I have array of connectors where I will plug in various types of resistors, I would like to be able to connect to each of the points as addresses and measure resistance between these points. Here is ...
0
votes
3answers
430 views
Why can't you use microprocessor I/O pins as chip enable pins for ROM and RAM?
I have been reading a textbook on Embedded systems called An Embedded software primer by David E Simon (great book btw). I am trying to answer questions after each chapter, I got through first 2 ...
2
votes
2answers
253 views
Understanding DDRn SDRAM
So I am basically trying to grasp/confirm my grasp of SDRAM and DDR. So basically I understand that there is going to be some chips each with up to 8 banks (so kinda like 8 chips internally?). For ...
0
votes
1answer
736 views
Proper way of storing a register address on ARM Cortex M4?
I am writing a program on STM32F4 Discovery where I have to store address of Timer's CCR register into a pointer and then change register via this pointer, ie
...
1
vote
1answer
1k views
What happens If the interrupt occurs during the execution of HALT instruction?
Consider the following program segment on a hypothetical processor .
I have this question in my course CS201.
Suppose this processor has 32 bits Load/Store operations, ALU operations is 16 bits and ...
0
votes
1answer
488 views
I2C address selection in PCA9685
I am using PCA9685 in a project. 3 are on the same i2c bus and thus I need to change the address of individual ICs. It has 5 selectable address bits as shown in the figure below:
The address will ...
1
vote
4answers
396 views
Clarification regarding I2C address
I was going through the following link which describes the "I2C address allocation table"
http://simplemachines.it/doc/IC12_97_I2C_ALLOCATION.pdf
Upon reading the aforementioned information table I ...
0
votes
1answer
67 views
Choose “safe” section of DDR memory in ZC702 board
I can not fully understand what section of the available external memory is safe to assign for a VDMA on the ZC702 board. I need to dedicate 4MB of memory for the three frames (640*480* 4bytes * 3 ...
0
votes
2answers
572 views
How to setup slave addressing with a HT16K33 in Proteus?
I have setup the following circuit in Proteus :
A PIC12F1822 is connected to a HT16K33 using an I2C bus.
I want to configure the HT16K33 to use the following address :
...
1
vote
2answers
154 views
considerations about little endian processor and opeartions on registers
Processor is little-endian.
Under followings addresses we have following values (hexdecimal format):
1000: FA
1001: 46
1002: 26
1003: C3
Now, processor is ...
2
votes
3answers
653 views
8086 memory decoder logic
I started creating a scheme for 8086 based computer now I'm in trouble with memory addressing.
I know a 20 bit wide addressing line can address up to 1024 KB of RAM and that pin A0, when high, select ...
0
votes
2answers
360 views
Is this address decoding circuit correct?
The problem is to design an address decoding circuit for two 4Kx8 RAM chips at the 2050H . We have 16 address lines. So, for 4Kx8 RAM we need 12 address lines to address the memory. Remaining can be ...
3
votes
1answer
1k views
Managing I2C address conflicts with multiple MCP23017 on the same bus
I'm using a Raspberry Pi with the I2C master and I successfully wired 8 different MCP23017 chips, each with their respective addresses by setting the last 3 bits of their 7 bit addresses. They are all ...
1
vote
2answers
194 views
Big address space and small physical size?
The Intel D1000 MCU datasheet says:
The MCU has 4 kB of data flash and 32 kB of code flash. Code flash
occupies the address range 0x2000 0000 to 0x3FFF FFFF and is aliased
throughout. It is ...
16
votes
2answers
972 views
4-bit bus address selection via analog input pin: Monte Carlo simulation shows overlapping address values
I designed a small sensor PCB for my master thesis with an ATtiny44 microcontroller. I need about 200 of these boards for my application and 16 are always locally connected to controller board. The ...
2
votes
1answer
165 views
How do I2C modules select between more than 2 slave addresses?
I am using the TMP112 I2C temperature sensor and noticed that you can choose between 4 slave addresses by connecting the A0 pin to V+, GND, SCL, or SDA.
How does the sensor tell between SCL, SDA, and ...
-1
votes
1answer
264 views
A computer system has RAM of 32K bytes and 64 peripherals. What is the number of distinct addresses required? [closed]
Is it correct to assume that the number of addresses for 32k of ram is 2^15 addresses? Then for the peripherals is it 2^6 addresses?
1
vote
1answer
69 views
MSP430 - how to check addressing types
I'm programming a MSP430 in C language as a simulation of real microcontroller. I got stuck in addressing modes (https://en.wikipedia.org/wiki/TI_MSP430#MSP430_CPU), especially:
Addressing modes ...
-2
votes
2answers
128 views
ECE - Study Guide: Physical Memory addresses how many bytes?
Attempting to do this study guide, but i'm not finding too much help online. Any help is welcome, and a explanation would be nice, as my text book does not describe how to answer a problem given the ...
1
vote
1answer
883 views
What's the difference between passive matrix and active matrix?
Both passive matrix and active matrix use "m+n" row-column addressing method to eventually switch individual components. So what makes one active and the other one passive?
1
vote
2answers
735 views
Problem with glue logic/memory decoding on a 6502 project
I have a problem understanding the following schematic, specifically the "Glue Logic(Memory Decoding)" section in the lower half middle:
This is a simple breadboard computer based on a 6502 CPU with ...
2
votes
2answers
10k views
What is the difference between full and partial address decoding?
Could someone please explain the difference between full address decoding and partial address decoding?
I am reading the chapter on digital logic in "Structured Computer Organization", 6th ed. by ...
1
vote
3answers
261 views
PIC24FV Reset without Flag
I am working on building an interrupt based program flow using the PIC24FV32KA302 module from Microchip. However, I am having some trouble with intermittent resets (it seems).
I am currently using ...
0
votes
1answer
546 views
What are the addressing modes of these avr commands?
What are the addressing modes of ldi, ld, and st. I think ldi is register direct, ld is register indirect, and st is also register indirect. Are those the right addressing modes?
0
votes
1answer
735 views
What are the CPU activity steps for the fetch-decode-execute cycle
So in all the phases of the fetch-decode-execute cycle, it says that the "store" phase is used to store any resultant data from the execute phase. What are the CPU steps for that phase? I heard that ...
0
votes
2answers
2k views
How many addresses are required for this system?
If a system has RAM containing 16K bytes with each of them needing their own distinct address and on top of that it has 16 peripherals and they each require 2^4 distinct addresses, then how many total ...
0
votes
1answer
106 views
Read and Identify Memory Diagram
I am so confused, and the book's explanation confuses me more, can anyone explain how to get and identify the following questions displayed? the Book talks about a 2^2 * 3 bit memory but I cant seem ...
