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What AMBA version do STM32F1, STM32C0 and STM32U0 have? [closed]

I can't find in any document what is the version (AMBA2, AMBA3 or else) of the AMBA bus have STM32F1, STM32C0 and STM32U0 MCUs. Is this classified information or can it be found somewhere?
Arseniy's user avatar
  • 2,239
2 votes
0 answers
43 views

How to understand "Only undefined length bursts can have a BUSY transfer as the last cycle of a burst"?

This sentence comes from AMBA AHB Protocol Specification(IHI 0033C) page 3-30. https://developer.arm.com/documentation/ihi0033/c/?lang=en For my understand, if the AHB manager launch a write operation ...
benjstark's user avatar
0 votes
1 answer
251 views

How to monitor the HWDATA and HRDATA in AHB-LITE on the all clock?

I'm trying to monitor the HRDATA and HWDATA on the AHB-Lite bus transfer. The monitor message should only appear when a command(...
Carter's user avatar
  • 607
0 votes
1 answer
105 views

What causes this "stuck address" behavior in STM32 peripherals?

I recently overcame an issue while writing some startup assembly for the STM32G474, which had to do with each peripheral having a "clock enable" bit that needs enabled before the peripheral ...
Aaron Linnell's user avatar
0 votes
2 answers
167 views

Clarification about Memory Address

I've been working with a project regarding an SRAM Controller in Verilog. As you can see, my controller should include those blocks. I've written some Verilog Code and right now I'm trying to test it, ...
Giuseppe Trematerra's user avatar
0 votes
1 answer
756 views

Why is data delayed by 1 clk cycle in AHB write transfer?

Here is a timing diagram showing a basic write transfer: The HWDATA comes 1 clk cycle after the control signals and the address. Why is this so? What will happen if the HWDATA is put on the bus at ...
gyuunyuu's user avatar
  • 2,053
0 votes
1 answer
770 views

Data during AHB Busy state

I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave: ...
x7ktrz's user avatar
  • 23
2 votes
1 answer
292 views

How does the Cortex M0+ processor use the AHB-Lite interface to fetch instruction and data?

How does the Cortex M0+ processor use the AHB-Lite interface to fetch instructions and data? Are instruction fetches done always using NONSEQ? How does it fetch data from memory (using burst or NONSEQ ...
Vignesh Dhamotharan's user avatar
1 vote
0 answers
186 views

Is it legal to design an open source AHB master?

Is it legal for open source cores to be compatible with the AMBA specification?
user avatar
-1 votes
1 answer
744 views

STM32F4 bugs in DMA, is there bug-free version?

Producer has confirmed that if there will be concurrent AHB and APB2 transfers using DMA2, then data corruption will occur (source). The bug discovery is from 2012, many years ago. Is the STM32F4 ...
Gortu's user avatar
  • 11