Questions tagged [alu]

ALU is the acronym for arithmetic and logic unit. This circuit performs arithmetic and logic operations in a processor.

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My 1-bit ALU is not able to do subtraction [closed]

I am trying to make a 4-bit ALU in Verilog which can perform the following functions: Add Subtract Compare (>,<,=) AND The approach I have taken is to make 4, 1-bit ALUs and connect them in ...
Koustubh Jain's user avatar
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Why does the Fused Multiply Add CSA use the inverted MSB of the addend when one multiply operand is negative?

I found one valuable paper about the "Fused Multiply Add": Instead of using 161-bit CSA, Only the 106 least-significant bits of the aligned A are needed as input to the 3:2 CSA, because the ...
An5Drama's user avatar
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Alu Control output not return 010 for Addi instruction

I'm currently working on a project for a MIPS Datapath Simulation website. The project aims to demonstrate how instructions work. I've implemented the Alu Control Unit using the combinational logic ...
Phronesis's user avatar
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How do we get a -1 in a 1-bit ALU?

In the 1-bit ALU and the table that is shown below, as you can see, the output is -1 when F0 = 1, F1 = 1, ENA = 0, ENB = 0, INVA = 1, INC = 0. The table is taken from a book (Structured Computer ...
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32 Bit FileRegister with ALU

Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable. It should be like figure1 below. I'm ...
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Where does the first carry-in go on a adder/subtractor circuit?

I am building a 4-bit adder/subtractor circuit using only logic gates on a breadboard. The following IC chips are being used: XOR- 7486, AND - 7408, OR - 7432. I have the full adders working fine. ...
Michael Paxinos's user avatar
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What is meaning and significance of locally decrementing SP (Stack Pointer)?

What is meaning of line "SP (Stack Pointer) can be decremented locally" *I am not asking the answer of the whole question in the image.
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Single-cycle ARM processor (flags)

This is an ARM processor from my book: The picture can be enlarged by clicking on it. I'm wondering about the control unit below, specifically the last picture, the conditional logic. Is the ...
user394334's user avatar
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How to do signed 16-bit arithmetic on an 8-bit processor?

For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output. This strategy falls ...
Max Zabarka's user avatar
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Can circuit without memory give output depending on the order in which input pins were activated for non-commutative operations?

Going trough making small NAND based computer. I have two input pins zy (zero 16 bit Array y), ny (negate bitwise 16 bit Array y). Implementing each one separately or in connection is no problem but ...
Andrey Sergeev's user avatar
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How much energy does it take to schedule versus execute a CPU instruction?

One of the justifications for vector instructions is that in a modern CPU, it takes more work to decode an instruction and do all the administrative work around it – scheduling, register renaming and ...
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How is sll implemented in MIPS?

I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
kene02's user avatar
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For a mathematical operation in CPU, could power consumption depend on the operands?

Obviously, the number of operations affect a CPU's power consumption, but does it solely depend on the operations themselves? For example, adding 0 and 1 involves setting one single bit, but adding ...
polfosol's user avatar
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How can I make a 7-segment display driver immune to intermediary states using basic logic gates (where each gate has a 1hz refresh rate)?

How can I make a hexadecimal 7-segment display driver immune to intermediary states using basic logic gates (where each gate has a 1hz refresh rate)? The problem I'm running into is that on the first ...
Dark Goob's user avatar
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Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?

The book But How Do It Know? presents an 8-bit computer architecture in which arithmetic-logic instructions (that is, instructions which are executed by the ALU) have 1 as the most significant bit, ...
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ALU 74181 Cn+4 output

I am a mathematician, so please forgive my wrong terminology :) I am currently trying to build an 74181 ALU and went over the schematics. On Wikipedia it is given as: https://en.wikipedia.org/wiki/...
Sebastian Mueller's user avatar
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Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?

I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from ...
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Logisim: Implementing a control unit for "Addition", "Logic bitwise AND" and "right logic shift" in ALU [closed]

I'm very new to circuit design. I've built an ALU and now I only need a control unit for three operations, "Addition", "Logic bitwise AND" and "right logic shift". What ...
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In a CPU, how are LU inputs/outputs controlled and fed back to registers?

Basic problem: CPU instruction chooses which register to feed into a LU (such as an ALU), which then outputs a number somewhere and fed back into a register. But sometimes you want to feed the answer ...
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Checking Bitstring for == 0, then set a zero bit = 1 in ALU

I am trying to model an ALU to implement a shift operation. When the shift operation is done, I should check if the result is 0. If a result == 0 is found, I want to set a single result bit to 1. I ...
oxicod's user avatar
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How are irrational numbers best represented and processed by computers?

My question is closely related to this one: How do computers understand decimal numbers? However, that question deals with rational numbers only. I was wondering if irrational numbers can be ...
Shashank V M's user avatar
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Role of ALU in executing MOV instruction

1.What is the role of ALU in executing instructions such as MOV, SET bit, Reset bit which doesn't require any computational feature of ALU? 2.Arithmetic part of ALU makes use of logic gate combination ...
Deepak Kumar's user avatar
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VHDL code for ALU and ROM connection

I need to connect an ALU with a two-port data memory, but I can only implement this far, and I don't know what is missing, plus I am a bit confused as to what to write for the testbench code ...
xxs899's user avatar
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Parallel execution in a single ALU

I read that in theory, it is possible to use the circuits in an ALU in parallel. Now I am wondering whether there is any way to leverage this in practice on commodity CPUs? Specifically, I want to ...
cabeer's user avatar
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How to compare two operands that are more than 4 bits using a 74181 ALU?

I have this 74181 ALU in Proteus. I want to compare two operands that are 8 bits. How should I change my circuit?
Mahdi Aspanani's user avatar
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ALU result is 0, how to fix this?

In system-verilog I am trying to build a small ALU unit which takes a and calculates the negative value of it (-1) in a CPU. I wrote: ...
josh's user avatar
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Would this type of design be scale-able? [closed]

With current technologies within a modern system, we have pushed the limits of computations within the CPU portion of the system where it now exceeds that of the memory units. Moving memory is slow ...
Francis Cugler's user avatar
2 votes
2 answers
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Connecting potentiometer to an FPGA simply

I have a question about connecting a potentiometer to a FPGA. I am connecting a potentiometer to an external 8 bit ADC chip that is outside the FPGA. I want the pot to represent a speed setpoint ...
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Can two x-bit ALUs/FPUs be combined to create an equivalent a single 2x-bit ALU/FPU?

I was wondering, can 2 16-bit ALUs/FPUs be combined to create a 32-bit ALUs/FPUs, or are 4 ALUs/FPUs required? I was wondering if lower precision ALUs/FPUs can be combined in any way to create a ...
itisyeetimetoday's user avatar
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Are FPUs made of ALUs, and how many ALUs are needed to make up an FPU?

In GPUs/CPUs, are FPUs made up of ALUs? If not, what would be a smaller "logical unit" that FPUs are made up of? If FPUs are made up of ALUs, how many ALUs would it take to make up a 16-bit ...
itisyeetimetoday's user avatar
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Sum of two 4-bit and a 5-bit number with 74181 ALU any advice?

I was designing a medium logic circuit and when trying to figure out this equation with 74181 ALU, I couldn't really find anything about how to make this work with a 4 bit ALU. equation F= 2A + B ...
tolgaocal80's user avatar
1 vote
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Can I implement addition and subtraction in different operations using a MUX?

I'm building a 16-bit ALU that needs to be able to perform logical AND, OR, add, subtract and rotate one bit to the left. I need to have addition and subtraction operate with different op codes ...
Matt L.'s user avatar
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1 answer
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How do I implement a rotate left 1 bit operation in a 16-bit ALU in logisim

I'm creating a 16-bit ALU that has to perform logical AND, logical OR, addition, subtraction and rotate left one bit. I have everything working perfectly except the rotate left one bit. I think I need ...
Matt L.'s user avatar
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4 votes
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What parts/sections of a CPU take the biggest number of transistors?

I was surprised to hear CPUs only have a number of ALUs. What are most of the transistors in a CPU dedicated to?
master_of_privates's user avatar
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Not getting correct results displayed from register

I am trying to input the numbers 1,0,3,2,32'hFFFFFFFF,32'h00000001 into the registers 0,1,2,3,6, and 7 respectively. I am doing this through always @(posedge clk) ...
TheBigBoyOverThere's user avatar
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How to instantiate module with variables

I declared alu_result as a reg because I need it to be a variable data type for my case statement. But when i do this, I cannot pass it my ...
TheBigBoyOverThere's user avatar
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1 answer
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Logical Effort in complex circuit - Output capacitance

As part of a VLSI course I was asked to estimate the delay of an ALU, similar to the one described in the picture, using Logical Effort method. I calculated the delay of the critical path through the ...
Alexey Kiryushkin's user avatar
2 votes
1 answer
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How does a processor negate an integer?

I am aware of three ways to negate an integer using 2's complement representation. The standard "invert, then add 1" which is taught in most textbooks. Scan from the least significant bit, ...
Barry Brown's user avatar
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Are there consumer ALUs in the GHz range?

When browsing consumer ICs, I struggle to see parts that function faster than a few hundred MHz, let alone in the GHz range. (Mostly the chips I want are ALUs or something similar.) Obviously ...
Samuel Clay's user avatar
2 votes
4 answers
111 views

Do ALUs perform all/most N operations before running through the multiplexer?

I'm doing some self-study on hardware and currently implementing an ALU. The way I'm designing it is such that I have an N:1 MUX (N inputs yield a single output (16 bit number) based on selector bits)....
Ryan's user avatar
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Syntax error near "else" in Verilog, in an initial block, next to assert

I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have: ...
Blucario's user avatar
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How do I implement a Barrel Shifter?

I'm using Multimedia logic for this particular assignment, I am to implement an ALU that performs Bitwise Rotation on the input from "A" by the amount defined by "B". Not quite sure how to approach ...
Enscivwy's user avatar
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Is a 14((n^2)÷2) gate n-bit integer divider reasonable?

I figured a way to implement a fast divider (basically a ripple-carry divider) with deterministic delay, but it's stupidly-large, essentially requiring two AND gates (multiplier and a position test to ...
John Moser's user avatar
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2 answers
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I have a problem with understanding the attached ALU (6 control bits)

I have an Arithmetic Logic Unit, as shown below (I also included a CircuitJS simulation of it, so it will be much easier to understand the inner working of said ALU). ‘x’ and ‘y’ are the 4-bit input ...
KamilWitek's user avatar
1 vote
2 answers
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Buses and the ALU in the 8086

Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5): If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
obe's user avatar
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9 answers
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What is the process of going from machine code to electrically controlling individual transistors? [closed]

For someone who writes software but doesn't have a computer engineering background, the dozens of abstraction layers have always bewildered me. I know all source code in their most fundamental level ...
master_of_privates's user avatar
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4 Channel NOT and AND Gate Symbols

I am designing an ALU for my computer architecture class. The rubric states that we need to simplify each logical part to make it as clear as possible. My group condensed the 4 NOT gates and 4 AND ...
Stephen Collins's user avatar
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2 answers
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How many ALUs (and threads) are in a Pentium CPU?

I'm reading a book bottom up where it said: The Arithmetic Logic Unit (ALU) is the heart of the CPU operation. It takes values in registers and performs any of the multitude of operations the ...
Marisha's user avatar
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Designing a Carry lookahead unit using EEPROMs, creates oscillator

I have read something about CLUs (Carry Lookahead Units) and want to build one. I have settled on a design using EEPROMS as ...
Kralik_011's user avatar
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when and how is the machine language (binary stream) mapped to an existing instruction?

I'm trying to better understand the entire process of coding, which involves translating the higher level languages (c++/java/python and so on) into binary data that tells the CPU to execute ...
dreamer's user avatar