Questions tagged [alu]
ALU is the acronym for arithmetic and logic unit. This circuit performs arithmetic and logic operations in a processor.
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Not getting correct results displayed from register
I am trying to input the numbers 1,0,3,2,32'hFFFFFFFF,32'h00000001 into the registers 0,1,2,3,6, and 7 respectively. I am doing this through always @(posedge clk) ...
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1answer
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How to instantiate module with variables
I declared alu_result as a reg because I need it to be a variable data type for my case statement. But when i do this, I cannot pass it my ...
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1answer
22 views
Logical Effort in complex circuit - Output capacitance
As part of a VLSI course I was asked to estimate the delay of an ALU, similar to the one described in the picture, using Logical Effort method.
I calculated the delay of the critical path through the ...
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Hardware Multiplication ALU
I have multiplicand 5 , multiplier 7 which they are binary representation :
5 = 0101 , 7 = 0111 (4-bit)
Register A to save the data to be multiplied(Multiplicand).
Register B to save the multiplier ...
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1answer
204 views
How does a processor negate an integer?
I am aware of three ways to negate an integer using 2's complement representation.
The standard "invert, then add 1" which is taught in most textbooks.
Scan from the least significant bit, ...
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1answer
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Are there consumer ALUs in the GHz range?
When browsing consumer ICs, I struggle to see parts that function faster than a few hundred MHz, let alone in the GHz range. (Mostly the chips I want are ALUs or something similar.)
Obviously ...
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3answers
41 views
Do ALUs perform all/most N operations before running through the multiplexer?
I'm doing some self-study on hardware and currently implementing an ALU. The way I'm designing it is such that I have an N:1 MUX (N inputs yield a single output (16 bit number) based on selector bits)....
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1answer
33 views
Syntax error near “else” in Verilog, in an initial block, next to assert
I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have:
...
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47 views
How do I implement a Barrel Shifter?
I'm using Multimedia logic for this particular assignment, I am to implement an ALU that performs Bitwise Rotation on the input from "A" by the amount defined by "B". Not quite sure how to approach ...
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Is a 14((n^2)÷2) gate n-bit integer divider reasonable?
I figured a way to implement a fast divider (basically a ripple-carry divider) with deterministic delay, but it's stupidly-large, essentially requiring two AND gates (multiplier and a position test to ...
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1answer
118 views
I have a problem with understanding the attached ALU (6 control bits)
I have an Arithmetic Logic Unit, as shown below (I also included a CircuitJS simulation of it, so it will be much easier to understand the inner working of said ALU).
‘x’ and ‘y’ are the 4-bit input ...
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2answers
116 views
Buses and the ALU in the 8086
Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5):
If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
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What is the process of going from machine code to electrically controlling individual transistors? [closed]
For someone who writes software but doesn't have a computer engineering background, the dozens of abstraction layers have always bewildered me.
I know all source code in their most fundamental level ...
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2answers
69 views
4 Channel NOT and AND Gate Symbols
I am designing an ALU for my computer architecture class. The rubric states that we need to simplify each logical part to make it as clear as possible. My group condensed the 4 NOT gates and 4 AND ...
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2answers
359 views
How many ALUs (and threads) are in a Pentium CPU?
I'm reading a book bottom up where it said:
The Arithmetic Logic Unit (ALU) is the heart of the CPU operation. It
takes values in registers and performs any of the multitude of
operations the ...
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1answer
53 views
Designing a Carry lookahead unit using EEPROMs, creates osclillator
I have read something about CLUs (Carry lookahead units) and want to build one. I have settled on design using eeproms as adders ...
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3answers
124 views
when and how is the machine language (binary stream) mapped to an existing instruction?
I'm trying to better understand the entire process of coding, which involves translating the higher level languages (c++/java/python and so on) into binary data that tells the CPU to execute ...
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6answers
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Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?
I was reading this very interesting question on Stack Overflow:
Is integer multiplication really done at the same speed as addition on a modern CPU?
One of the comments said:
"It's worth nothing ...
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1answer
180 views
Microprocessor architecture bits vs bus sizes
I am ready following on this website:
"Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
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1answer
51 views
Choosing the best approach for data selection in a datapath
For a university project, I have to design and construct a very simple CPU including the ALU.
In order to select between different data lines that go into the ALU(32-bit data line), I have thought of ...
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2answers
76 views
How does a computer know when to “get” the output from the ALU?
Basically what the title says, I guess I've got some sort of misconception or somthing probably. The ALU can have, say, a ripple carry adder which doesn't produce its entire output all at the same ...
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1answer
148 views
ALU Design in verilog HDL
Below is my code for ALU which instantiates a 4:1 MUX and a 32 bit squarer modules. The port connections can be seen in module instantiations. However it is important to mention here that input of MUX'...
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122 views
Parallel Prefix Adder explained
I think I have understood Carry Lookahead adders.
However, I don't really understand how parallel prefix adders evolve from carry lookaheads. Can someone explain to me the difference between PPA and ...
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1answer
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Designing a 2-bit ALU [closed]
I want to design a 2-bit ALU that does XOR, OR, AND, and addition.
With help of Wikipedia:
I designed this:
However, it's not working.
I tried connecting the controllers to S0, S1, S2 but no ...
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3answers
364 views
Why does a full adder need an OR gate?
I have read and I understand how the full adder works (or atleast I think I do :D). It combines two half adders and either one of them can have a carry over, hence the OR gate. But why do we need ...
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1answer
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Do binary numbers move in sequence ones and zeros or parallel at once to ALU for addition?
Do binary numbers move in sequence ones and zeros or parallel at once to ALU for addition, I mean ones and zeros in sequence vertically to ALU or parallel horizontally AT ONCE?
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How to get the MSB into a logic gate which will check if a number is negative or not?
I need to create a logic gate which will find out whether a number is negative or not.
The input is 8 bits and the output is 1 bit, and if the input is 1 (i.e. negative number) then the output ...
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1answer
614 views
How to find out if the input of a logic gate is negative in two's complement?
I'm trying to create something which will output whether the input of the logic gate is a negative number or not in two's complement. I understand how twos complement works etc, but i'm not entirely ...
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3answers
282 views
How to find out if a binary number is zero or not using logic gates?
I'm trying to put some logic gates together which would perform a task of finding out whether a number is zero or not. I came across a thread like this on here already (How to find out if a binary ...
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2answers
362 views
How to use comparator functions of 74LS181?
I'm experimenting with the 74LS181 ALU (see here if you like), and it is going well, but I am unable to figure out how to use the A=B, A>B, and A<B comparator functions.
The datasheet states, "...
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2answers
108 views
Are floating point numbers denormalised before the processor performs arithmetic operations on them? [closed]
Does the processor denormalise the numbers in IEEE 754 notation and normalise the result after storing or are the arithmetic operations performed on the numbers as they are?
I'm asking because in case ...
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366 views
What is the True Pinout and Function of the 74ls181 in both of its modes (Active High and Active Low)?
I've found several datasheets for the 74ls181 with pinout and function diagrams as pictured below.
This from Jameco (where I bought mine): https://www.jameco.com/Jameco/Products/ProdDS/46973.pdf
...
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2answers
238 views
Bus tapping in Xilinx ISE for 8 bit to 16 bit conversion
I have a processing unit which is controlled by a sequencer/control unit. The agenda of this processing unit is to multiply 2 numbers using 8 BIT registers using the bit shift and add method.
Once ...
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0answers
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Rom.txt in quartus prime [duplicate]
What is rom.txt in quartus prime? What does it do? How do you change it and implement?I’m building a 8 bit alu. Thanks
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1answer
572 views
Design on ALU in multisim
I am trying to design a simple 2 bit ALU which can perform addition, OR and XOR. Here's the picture of my design in multisim.
Problem with my design is i'm not understanding the purpose of select ...
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1answer
108 views
SN74LS181: The comparison function, A=B, not operating
I have six SN74LS181N-B circuits for arithmetic functions. I intend to utilise the A=B output, which is the comparison function. Sources have indicated that this function operates, if subtraction is ...
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1answer
154 views
Need help understanding the status output generation of an ALU
I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model.
The thing I can't understand is the ALU is generating a "status" ...
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2answers
202 views
Why is the inverter need in this ALU?
I'm studying computer architecture and I wonder why the inverter is needed in this ALU?
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216 views
Design of Arithmetic Section
While going through topic on ALU design. I came across the point.i.e Design of Arithmetic Section .But what confused me is what is it's purpose in ALU. I'm thinking it in terms of performing basic ...
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1answer
226 views
Why would ALU Output be Asynchronous with Input Change?
Wikipedia states "An ALU is a combinational logic circuit, meaning that its outputs will change asynchronously in response to input changes."
But, the definition of a combinational logic circuit is: "...
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347 views
Why are ALUs still serial?
One of the most common optimizations used in modern processors is to keep the silicon as busy as possible. Cache units access memory for the processor so other circuitry isn't tied up for the dozens ...
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1answer
558 views
Why is the output to this 74181 ALU circuit always on?
I recently built an ALU circuit using the 74181 4 bit ALU. The circuit I built is below:
simulate this circuit – Schematic created using CircuitLab
Please note that the pinout in the ...
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1answer
733 views
2 x 74LS181 4 bit ALU's cascaded to form 8 bit ALU, Cin problem?
When trying to add two numbers on my two cascaded 74LS181's I find that the result seems to be right when I tie the carry (Cn) of the least significant one to Vcc, contra my expectation that Cn should ...
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4answers
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74181 ALU not working properly cascaded to add 8 bit numbers
I'm trying to make a homebrew CPU but having problems with the 74LS181 ALU, which I'm simulating in Logisim software before diving into real ICs and breadboards.
I've cascaded two 74181 following ...
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1answer
150 views
In an ALU, is every function calcuated simultaneously?
I'm designing a 4 bit ALU as a project. I have circuits that can calculate addition, subtraction and bitwise logic operations - my question is, do I tie A & B (4 bit inputs) to every circuit that ...
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1answer
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Why don’t most RISC ISAs write integer MULH/MUL or DIV/REM to two general-purpose registers? [closed]
Most hardware multiplication and division algorithms can compute the high and low words of a product of two integers, or both the quotient and remainder of the division of two integers, at the same ...
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How to create Verilog or VHDL from a Quartus design
I have done a Quartus design from logical primitives for FPGA. Now I would like to see the corresponding Verilog or VHDL if feasible. Is that possible with Quartus and if so, how?
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ALU carry in/out
Say there is an ALU with 3 inputs (A, B, Cin) and 2 outputs (Res, Cout).
It has functions [A plus B, A minus B, B minus A, A or B, 0, 1].
From my understanding, this is how the carry-in/out work for ...
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3answers
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does 8085 CPU have an extra register within ALU?
From the 8085 CPU architecture, when ALU done calculation, the result is clocked back to accumulator A on next clock edge. But accumulator A is directly wired as ALU input, what if the clock edge didn'...
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2answers
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Which register holds the final arithmetic and logic results?
This Wikipedia page says
an accumulator is a register in which intermediate arithmetic and
logic results are stored.
So which register holds the final result?
