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Questions tagged [amba]

Advanced Microcontroller Bus Architecture

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Why does the AMBA APB bus need a PENABLE signal?

What is the purpose of the PENABLE signal of the APB bus? I understand that PENABLE signals that an address has been set on the PADDR bus. But, there are PSEL and PCLK lines. If the PSEL is set and ...
Arseniy's user avatar
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How to understand "Only undefined length bursts can have a BUSY transfer as the last cycle of a burst"?

This sentence comes from AMBA AHB Protocol Specification(IHI 0033C) page 3-30. https://developer.arm.com/documentation/ihi0033/c/?lang=en For my understand, if the AHB manager launch a write operation ...
benjstark's user avatar
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How to monitor the HWDATA and HRDATA in AHB-LITE on the all clock?

I'm trying to monitor the HRDATA and HWDATA on the AHB-Lite bus transfer. The monitor message should only appear when a command(...
Carter's user avatar
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Relationship between PSEL and PENABLE signals in the APB protocol

I would like some clarification on the relationship between the PSEL and PENABLE signals in the APB Protocol. The specification states: The PENABLE signal is asserted the following clock after PSEL ...
P Ksagar's user avatar
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axi4-stream data FIFO almost full without input

I am very new to FPGA/Vivado. I am trying to understand how does the IP AXI4-Stream data FIFO work. To simulate the producer, I connect the tdata and tvalid pin of the FIFO slave interface to all zero....
L.Han's user avatar
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AXI Stream Master - M_AXIS_TVALID not always be '1' during a transaction and M_AXIS_TLAST

I am implementing my AXI Stream Master module which can be use with Vivado DMA module. The connection of module is shown: I have 3 questions: 1.) Could the "m_axis_tvalid" signal be non ...
Yee Yang Tan's user avatar
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765 views

Why is data delayed by 1 clk cycle in AHB write transfer?

Here is a timing diagram showing a basic write transfer: The HWDATA comes 1 clk cycle after the control signals and the address. Why is this so? What will happen if the HWDATA is put on the bus at ...
gyuunyuu's user avatar
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How does a microcontroller development board use USB cable to transmit serial data?

I'm trying to understand every section of the journey of data from a microphone via a microcontroller to a pc terminal. I realize now after reading about serial data transfer that real-time audio ...
A.Davies's user avatar
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what triggers the PREADY signal in a slave of an APB?

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state? If anyone could help me with this basic ...
QTip's user avatar
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AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
Nazar's user avatar
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APB PENABLE stays only for one PCLK regardless of PREADY signal

I followed the AMBA 3 APB specification to design my APB slave. Reading from a slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
Nazar's user avatar
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What's the best internal SoC bus?

As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real ...
user37741's user avatar
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AXI Stream Pipeline

I have following design and need to insert pipeline stage between components A and B (design doesn't meet timing constraints in Quartus II due to long data path between them).. Simple register won't ...
David Novák's user avatar
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Is it legal to design an open source AHB master?

Is it legal for open source cores to be compatible with the AMBA specification?
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Connecting multiple AXI4-Lite slaves

When connecting several AXI4-Lite slaves, must I use some kind of interconnect? If it is guaranteed that each slave decodes a distinct set of addresses, is it possible that the slaves would set their ...
haggai_e's user avatar
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Why we can't use AHB in the Cortex M0 MCU?

I found coretex M0 MCU module's bus interface has not HBUSREQ and HGRANT, and HRESP when i trying to implement with AHB Bus. Is there any way to use AHB not AHB_lite. I can't use multi-layer ...
nashile's user avatar
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