Questions tagged [amba]

Advanced Microcontroller Bus Architecture

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How does a microcontroller development board use USB cable to transmit serial data?

I'm trying to understand every section of the journey of data from a microphone via a microcontroller to a pc terminal. I realize now after reading about serial data transfer that real-time audio ...
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In AHB (and other related buses), what is meaning of a “mirrored” master and “mirrored slave”, why is this required?

I think that an AHB master bus would connect to AHB slave bus, but it seems that is not the case. AHB master bus connects to AHB mirrored master and AHB slave connects to AHB mirrored slave. Is this ...
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28 views

what triggers the PREADY signal in a slave of an APB?

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state? If anyone could help me with this basic ...
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67 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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175 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
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123 views

APB PENABLE stays only for one PCLK regardless of PREADY signal

I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
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1answer
559 views

What's the best internal SoC bus?

As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real ...
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2k views

AXI Stream Pipeline

I have following design and need to insert pipeline stage between components A and B (design doesn't meet timing constraints in Quartus II due to long data path between them).. Simple register won't ...
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136 views

Is it legal to design an open source AHB master?

Is it legal for open source cores to be compatible with the AMBA specification?
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187 views

Connecting multiple AXI4-Lite slaves

When connecting several AXI4-Lite slaves, must I use some kind of interconnect? If it is guaranteed that each slave decodes a distinct set of addresses, is it possible that the slaves would set their ...
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157 views

Why we can't use AHB in the Cortex M0 MCU?

I found coretex M0 MCU module's bus interface has not HBUSREQ and HGRANT, and HRESP when i trying to implement with AHB Bus. Is there any way to use AHB not AHB_lite. I can't use multi-layer ...