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Questions tagged [amba]

Advanced Microcontroller Bus Architecture

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23 views

AXI Chip2Chip Addressing

I am using a AXI Chip2Chip master (with Aurora) on a MPSoC connected to a Xilinx Virtex UltraScale+ running a AXI Chip2Chip Slave. I have set the Master's to 0x10_0000_0000 with 1G of space, see pic ...
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1answer
56 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...
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1answer
66 views

APB PENABLE stays only for one PCLK regardless of PREADY signal

I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle ...
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1answer
254 views

What's the best internal SoC bus?

As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real ...
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1answer
1k views

AXI Stream Pipeline

I have following design and need to insert pipeline stage between components A and B (design doesn't meet timing constraints in Quartus II due to long data path between them).. Simple register won't ...
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0answers
130 views

Is it legal to design an open source AHB master?

Is it legal for open source cores to be compatible with the AMBA specification?
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1answer
149 views

Connecting multiple AXI4-Lite slaves

When connecting several AXI4-Lite slaves, must I use some kind of interconnect? If it is guaranteed that each slave decodes a distinct set of addresses, is it possible that the slaves would set their ...
1
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1answer
151 views

Why we can't use AHB in the Cortex M0 MCU?

I found coretex M0 MCU module's bus interface has not HBUSREQ and HGRANT, and HRESP when i trying to implement with AHB Bus. Is there any way to use AHB not AHB_lite. I can't use multi-layer ...