Questions tagged [architecture]

As used in EE.SE, it describes the physical topology and techniques of routing power, ground, data and control lines across a given area. This could be a CPU/MPU, circuit board or the lighting of LED's around a pool. Electrical parameters and physical (object) constraints ultimately decide the most efficient and safe layout. The term 'architecture' has no scale (size) until it is defined by schematics, diagrams, blue prints.

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Soft power-off compatible with two different hardware architectures

I've been tasked with designing a single PCB that will (amongst other) provide soft-power off feature to two different products with different hardware architectures. The notable differences between ...
Lars Petersson's user avatar
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How to get USB 3.x power but with data limited to USB 2.0 HS?

I am designing a device with a few interesting requirements. Due to power requirements, we need to draw 900mA, but due to isolation requirements, we're limited to the 480Mbps rate for our primary ...
mbengineer's user avatar
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Is there a specific meaning for these arrows in the architecture of a microcontroller?

Yellow mark Green mark Blue mark Do these arrow signs mean something specific? Also, if there are other types, where can I go to read about them? Source : here Edited :
Just doin Gods work's user avatar
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How do you fit so many instructions on a 8-bit processor?

I will preface this that it is highly likely that I have misunderstood how Harvard architecture works, but I cannot understand how an 8-bit instruction set, say the ATmega128 for example, can contain ...
Lyndon Alcock's user avatar
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1 answer
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ADS8598S - how to connect to a MCU - general Architecture question

For a future project I'd like to use the ADS8598S from Texas Instruments, which is a "higher speed" 8 Channel simultanously sampling ADC with 18 Bits and a max. Sample rate of 200 kSPS per ...
pm4812's user avatar
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How do 16-bit addresses work inside 8-bit data bus processors?

As a project I am building a small 8-bit RISC processor out of discrete ICs. I have 17 instructions and cannot fit all information into instructions that are only one byte, so I have been thinking ...
David777's user avatar
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11 votes
3 answers
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Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?

Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.) The thing I do not understand is that why we see only one memory address space. For example, in tge ...
gvg's user avatar
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?

By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation. Hence, are coarse-grained ...
Giovanni's user avatar
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Power outage detection to kickstart a safe shutdown and data retention process

I plan a system that operates on a 5v rail. The power is supplied from an outside DC source. The 5 V powers an RPI CM4 and other components that are controlled by it. The whole system requires up to 5 ...
metsik's user avatar
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2 answers
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Soft errors from SEUs/SETs in early 8-bit microprocessors?

Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
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Help needed in selecting the power architecture for my project [closed]

I had some trouble in finalizing the power architecture for my upcoming project. In a brief summary about the project, I am using a GPS device to acquire location of the vehicle and control two ...
Rohit_Kashyap's user avatar
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2 answers
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What are common ways that modern processors handle data hazards with asynchronous registers

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it. Specifically, I'm implementing control and status registers (CSRs), which ...
tuskiomi's user avatar
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1 answer
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Software for system architecture capture

I work as an electronics engineer and I'm starting to create a new device. This device will be significantly more complex than any project i've undertaken so far and will require close interaction ...
benp's user avatar
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4 votes
2 answers
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Electronic Controller Unit (ECU) Vs. MCU

Isn't the Electronic Controller Unit (which are used in automotive applications) a Microcontroller it self? What is the difference between them in architectural point of view?
Lavender's user avatar
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IA 32 architecture segmentation

I was reading the 10th edition of "Operating System Concepts" written by Abraham Silberschatz and many others. It says about IA-32 architecture's segmentation: The IA-32 architecture allows a ...
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3 answers
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CPU no pipeline vs 1 stage pipeline

I was taking the the P.E. practice exam and there is a question that shows a CPU without pipeline stages. There were options for both a 1 stage pipeline or that it was a non-pipelined architecture. ...
Eric Johnson's user avatar
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4 answers
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Should I get rid of my bias towards active high?

I realise that in all my circuits I consider active-high the "natural" default and active-low a goofy situation that needs to be inverted. I pull down all data and control lines (resets, output enable,...
Zsolt's user avatar
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What is the difference in VHDL between multiple architectures and multiple generate statements within one architecture?

Considering two cases: Case 1: A top file where, depending on a parameter P, I make use of the generate statements to ...
Amnay's user avatar
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7 votes
9 answers
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What is the simplest instruction set that has a C++/C compiler to write an emulator for? [closed]

I'm looking into writing a little software emulator that emulates/runs instructions. The easiest would be to invent my own instruction set, but I thought it would be more fun if I write an emulator ...
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1 vote
4 answers
420 views

How does a computer know when to "get" the output from the ALU?

Basically what the title says, I guess I've got some sort of misconception or somthing probably. The ALU can have, say, a ripple carry adder which doesn't produce its entire output all at the same ...
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3 answers
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Embedded Architecture [closed]

The most common idea on 'new age' embedded devices - IoT Devices is using an Arm Cortex (Mostly M Series) processor as Central Unit and some Sensors and Peripherals for acquiring data and metrics (...
Ioan Kats's user avatar
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2 answers
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How to select the most appropriate (serial) bus for controller?

In the context of a robotic project where different 'payloads' and/or robotics arms (end-deflector) should be mated mechanically with power, data and control connections support, I would like to ...
bli's user avatar
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1 answer
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Non-isolated DC power distribution for an appliance

I am building an appliance where we have a device where we need to have a +48 V/300 W DC power rail and a +24 V/300 W DC power rail. The AC (mains) should be world-compatible (both low- and high- ...
HW2015's user avatar
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AI hardware architecture

I am looking for more info on AI hardware architectures, but I am a bit confused. Here are my questions: Does it all come down to MACs(Multiply And Accumulate) units? Do MACs usually integrate into ...
Aleksandar Kostovic's user avatar
3 votes
3 answers
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Why is there a system controller and a microcontroller in the same FPGA?

I am starting to dig into the FPGA world. While exploring the FPGA SmartFusion2 architecture I found out that there is a microcontroller (ARM Cortex-M3) and at the same time a system controller. Why ...
Lavender's user avatar
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1 vote
1 answer
81 views

How is pipelined DES different from sequential DES?

I implemented DES (Data Encryption Standard) Coder in VHDL using ISE IDE by Xilinx in sequential architecture which was pretty easy and straightforward. Now my task is to do the same using pipelined ...
Filip Mazi's user avatar
6 votes
2 answers
6k views

What is a Programmer's Model?

The manual of a computer processor usually includes a description of something called programmer's model. This section normally presents the core registers of the processor, operating modes, ...
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1 answer
576 views

Internal physical layer in microcontrollers

I am working on a project and while doing the component selection I realised that many microcontrollers have MAC & PHY layer on the different chip. Except for TM4C1294 microcontroller (there might ...
Mayank's user avatar
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2 answers
180 views

If a flip-flop D is given in input D = 1 when the clock is C = 1

If a flip-flop D is given in input D = 1 when the clock is C = 1, and then, when the clock becomes C = 0, D = 0, what will be the status eventually assumed by the flip-flop? Will it be 0?
Jonsa's user avatar
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4 answers
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How is the code written in ARM7 compatible with ARM9?

I'm studying ARM families, In the above image, it is written that the code by supported ARM7 can be migrated to ARM9 and others. ARM7 uses the Von-Neumann architecture (single bus for data and ...
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12 votes
5 answers
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PIC32 vs dsPIC vs ARM vs AVR, does the architecture matter when we are programming in C-language anyways? [closed]

We are currently using 32-bit PIC32 Microcontroller. It is working fine for our needs, but we are also exploring other microcontollers that can suite us better + we have other projects for which we ...
TheTechGuy's user avatar
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1 answer
65 views

Step-down voltage directly or in intermediate steps?

Couldn't make up my mind :P Characteristics: 12V-80V Vin (DC) 3.3V system In general terms (considering architecture and design) is it better to do directly 3.3V from Vin or is it better to do ...
crypton's user avatar
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1 vote
4 answers
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Replace ALU With Lookup Table? [closed]

Disclaimer: So this is obviously a silly question and I want to start by saying I don't want to discuss the financial costs of this, as I'm aware CPU cache is expensive. As this hasn't been made ...
Greg Hilston's user avatar
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2 answers
206 views

What affects the design of a SOC or uC to offer XIP or RAM for code execution

I have been trying to understand the factors in controller / SoC design such that it can execute code from either XIP flash or from a RAM. There are controllers that support an XIP flash of around 5MB ...
nkvvj's user avatar
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4 votes
1 answer
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unconnected line (xx,yy) to (XX,YY) - Altium designer

Newbie in Altium designer here. I have read the online documentation from Altium, however, I still have a warning when trying to compile my schematic in Altium: my schematic: The warning says: ...
LandonZeKepitelOfGreytBritn's user avatar
8 votes
3 answers
3k views

What actually happens when we set direction on GPIOs in controllers ?

Generally, while working on GPIO pins of any controller/device, we set the directions for the GPIO pins. Let's say in LPC2148(ARM7 core) controller, we have IODIR to configure the direction of Pin. We ...
GShaik's user avatar
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-1 votes
1 answer
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What is an architecture?

I've read many times the terms: cpu architecture hardware architecture software architecture computer architecture And so I thought an architecture describes the structure (layout,interface, ...
Jorgos's user avatar
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11 votes
2 answers
11k views

What type of processor in usual 8-digits pocket calculator?

There are a lot of +,-,*,/,CE,MC,M+,M-,MR buttons 8-digits calculators on market with keyboard layout like: ...
gavenkoa's user avatar
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1 answer
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project RT level using register [closed]

to every one. excuse my poor english. may someone help me resolve this problem. What does RT level means? A,B,C,D,W,X,Y and Z are register of n bit. project the RT level of this function just using on ...
ulrich hondje's user avatar
1 vote
2 answers
1k views

Difference between multiple pipelines and superscalar?

I have read some threads and the wiki articles, but still don't seem to understand what exactly the difference is between having multiple parallel pipelines and the superscalar architecture. I know ...
Benjoyo's user avatar
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0 votes
6 answers
3k views

how to know how many bits a microcontroller has?

How can I know what kind of architecture a microcontroller has? For example where can I read in the datasheet of the pic 16F873 how many bits architecture is? 8, 16, 32? Next question what does: What ...
Kevin's user avatar
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0 votes
2 answers
333 views

Can we declare output as "inout" to design a flip flop in VHDL?

I want to design a JK flip flop in VHDL. In this output depends on previous state. One method to implement this condition is by declaring a state as a signal inside the architecture. Another method ...
tollin jose's user avatar
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1 vote
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Example Instruction Set Architechture

Not entirely sure which stack site to post this question to, but I'll give this section a whirl. I have a question on my homework which reads as follows: Instruction Set Architecture. You are ...
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3 votes
1 answer
4k views

Serial communication best practices

I actually need to communication between my pc and a device using serial protocol through USB. I'm looking for some guidances and best practices and messaging architecture. Do you know any reference ...
Emmanuel Istace's user avatar
2 votes
2 answers
7k views

Why do some Integrated Circuits get so hot?

I was reading an article about Radeon 6990 recently and it was recommending 1200 Watts of power supply and the entire machine to be kept dipped in mineral oil because air cooling would kill it in a ...
Regmi's user avatar
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1 vote
2 answers
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Accessing an SRAM Array?

As im learning about Computer Architecture im trying to understand it from the ground up (Transistors in CMOS in particular) I came across the simple 6T schematic for SRAM (2 inverters) Mostly makes ...
user avatar
16 votes
3 answers
10k views

VHDL: Architecture naming and interpretation

Note: I am using Xilinx's ISE and have an FPGA board to work with (with switches and lights and so on), and I've hacked together some simple projects so far. At the same time I'm reading several ...
MartyMacGyver's user avatar
12 votes
4 answers
3k views

How does the Harvard architecture help?

I was reading about arduino and the AVR architecture and got stuck at the point that how does pipeline stall or bubbling is solved by Harvard architecture introduction in the AVR.I mean what Harvard ...
Ayush's user avatar
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3 votes
1 answer
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What is CLK in UART/USART used for?

I'm studying computer architecture at my university and I've been recently asked a question: what is CLK used for in UART/USART? The first obvious thing is that it is used for dividing frequency when ...
roman's user avatar
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4 votes
2 answers
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Sorting of data from instructions ( ARM I-cache and D-cache )

Some ARM cores like the ARM9 family of cores have a Harvard Architecture, at least at the cache level. That is they access two seperate caches, an I-cache for instructions and a D-cache for data ( ...
darbehdar's user avatar
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