Questions tagged [arithmetic-division]
Division of integer or floating-point numbers represented as bits. For analog division tag with [analog-computer] instead.
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How many bits are required for a quotient in binary division?
I saw somewhere that if we have A (dividend) which is 2n-bits and B (divisor) which is n-bit, we can store the quotient in n-bits with a specific condition: the (n-1)th bit of the divisor has to be 1.
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Remainder of a 16-bit number divided by 3
I have to design a combinational logic circuit which accepts a 16-bit number as input and then calculates the remainder of the number divided by 3 as its output.
I originally had no idea how to ...
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Divide by integer in VHDL
I need to divide an integer by an integer in one clock cycle.
How should I do this?
I have a function for it I found on the internet but it always returns one.
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How to implement division?
I'm creating an ALU for a simple calculator. I have made the addition, subtraction, and multiplication part of the ALU and with them I didn't have to initialize anything.
I am attempting to create the ...
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Signed Integer Division Optimization [closed]
I've implemented a division algorithm on an FPGA using the long division algorithm. My implementation does not use pipelining, but works iteratively and requires very few logic elements since the ...
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Choose the right strategy to divide two values [closed]
Info:
After getting some comments and already one answer, I decided to rewrite this question to better fit into this site.
I had a problem where I needed to downsize a 12 bit value to an 8 bit value. ...
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Fastest way to get integer mod 10 and integer divide 10?
If a hardware doesn't support modulus or division operations, it takes many more CPU cycles to simulate modulus/division by software. Is there any faster way to calculate division and modulus if the ...
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How does division occur in our computers?
How does division occur inside digital computers? What is the algorithm for it?
I have searched hard in google but haven't got satisfactory results. Please provide a very clear algorithm/flowchart ...
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Is it possible to build a binary divider with this design?
So I am working on this ALU, and I have made this 8-bit multiplier based on this design: . Is it possible to adapt this design into a binary divider by using Subtractors instead of Adders, and maybe ...
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Using the fast adders circuits in FPGA
Im confused on how to use the dedicated carry logic
The first image shows the schematic for a full adder using a MUX
It looks like one of the outputs are equivalent to A XOR B
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Binary division restoring method
Hi i need help in understanding the binary division restoring method
From -2, we stored the value to 5 by adding the divisor which is 7
After adding 7 to get 5, why does it automatically jump to 10?
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Why does signed (2's complement) binary multiplication have different procedure than unsigned?
The 2's complement binary multiplication does not have same procedure as unsigned if the both operands do not have the same sign. What is the logic behind that?
Does special consideration apply to ...
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How do computers understand decimal numbers?
Computers calculate numbers in 0s and 1s. A bit can be either but not in between. So if you enter 3/2 into a calculator, it should return either 1 or 2, right? Wrong! It gives you 1.5, the correct ...
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Why does hardware division take much longer than multiplication?
Why does hardware division take so much longer than multiplication on a microcontroller? E.g., on a dsPIC, a division takes 19 cycles, while multiplication takes only one clock cycle.
I went through ...
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Shift left followed by round for performing: y=x+cz in hardware
I wan't to implement a simple arithmetic, given the following (say 8 bits) integers x,y,z
$$y = x + c z$$
where 'c' is a fraction of a power of 2: 2^-1, 2^-2, 2^-3,...
I was adviced to perform the ...
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Is a 14((n^2)÷2) gate n-bit integer divider reasonable?
I figured a way to implement a fast divider (basically a ripple-carry divider) with deterministic delay, but it's stupidly-large, essentially requiring two AND gates (multiplier and a position test to ...
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Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?
When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
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Why overflows are omitted in the non-restoring hardware binary division algorithm?
I'm reading a book about a non-restoring binary division algorithm, for example 52_octal divided by 41_octal:
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How to divide complex number in VHDL?
I know how to divide numbers in VHDL (or using one of the Xilinx IP core generators) but I do not know how to do it in the case the numbers are complex.
In my case I have defined a complex number as ...
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Digital Multiplication, Subtraction, Division Integrated Circuits?
Having a hell of a time finding ICs that offer multiplication, subtraction and division?
Are these functions just a product of adders and not worth the fab?
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Why don’t most RISC ISAs write integer MULH/MUL or DIV/REM to two general-purpose registers? [closed]
Most hardware multiplication and division algorithms can compute the high and low words of a product of two integers, or both the quotient and remainder of the division of two integers, at the same ...
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SRT division vs Non restoring division
Assuming base b=2, is there a particular advantage in terms of performance when comparing SRT division to non restoring division?
In Non restoring division, for ...
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8051 24bit BCD division
I am currently working on a 8051 assembly program which receives a set of BCD inputs and calculates the mean of this set. However, I couldn't figure out a decent way to divide 24bit BCD number. For ...
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Verilog modulo without using "%"
I'm interested in Verilog, but I have a question. I tried to implement modulo without using '%` operator. So I made it this way:
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On-line arithmetic vs digit recurrence, are they different?
I'm looking at some reference to "On-line arithmetic",in chapter two of this PhD thesis there's a description of such methods. There's a recurrence derived at some point in such thesis that reminds me ...
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Can fixed point division be implemented using a divider that outputs quotient and remainder?
From what I have seen, division is a highly expensive operation in terms of time or area (tradeoff). It is usually implemented as an operation of continuous subtraction of a number from another number ...
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Using Three-state logic to speed up floating point multiplication
This question is idle pondering but...
Given "double-precision" is 53 bits, so takes 53^2 (or 2809) largely ordered sequential operations to perform multiplication. Whereas the equivalent ternary ...
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Division circuit
On the picture below is shown a circuit for arithmetic division. Can somebody please tell me how does it work? I am struggling to understand it as I am new to this area.
Note:
This is not a homework ...
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System Generator: How to configure the CORDIC divider block. Understanding the block parameters
I have some dudes about the block parameters of the CORDIC DIVIDER.
I would like to someone explain me the parameter called "Latency for each processing element".
(See the parameters inside the red ...
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Efficient inverse (1/x) for AVR
I'm trying to find an efficient way of calculating an inverse on an AVR (or approximating it).
I'm trying to calculate the pulse period for a stepper motor so that I can vary the speed linearly. The ...
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Dividing numbers on an FPGA
I wrote a program for a Cyclone II FPGA that divides 2 64 bit numbers and returns if the remainder is 0 using the modulus (%) operation.
When I compiled the program with 64 bit numbers for the ...
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I want to implement a math equation in FPGA, should I describe a CPU or can I do it just by code?
For a school project I'm trying to implement an equation for example like this:
(EDIT)
B = ((A + 2) * |A - 10|) / (c * c)
everything is unsigned binary values, ...
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hardware implementation of division algorithm
I have tried hard but I don't understand how this algorithm is working.Please explain the flow chart.
\$DVF\$ is the divide overflow flip flop.
\$A_s\$ is the sign bit of \$A\$
\$B_s\$ is the sign bit ...
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