Newest 'artix-series-fpga' Questions

0

votes

1answer

81 views

How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...

asked Feb 11 at 20:47

IgNite

177

2

votes

1answer

104 views

Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...

fpga spi vivado constraints artix-series-fpga

asked Nov 4 '18 at 3:26

CanisMajoris

2315

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1answer

80 views

single port 32x32 synchronous ram design using verilog in vivado hls

in the verilog code below: ...

verilog vivado zynq artix-series-fpga

asked Sep 26 '18 at 5:05

Shubham Choudhary

1

3

votes

2answers

230 views

Debounce on Nexys4 DDR button

I am trying to implement a simple UART transmitter, where the Nexys4 DDR board is sending ASCII characters to my PC, which I can view using Tera Term. The problem I am having is that when I press one ...

fpga vhdl artix-series-fpga

asked Jan 26 '18 at 19:29

nnja

161

1

vote

1answer

164 views

Is XADC synchronous in Artix 7 Series FPGA?

I was wondering if the output data of the XADC in the Basys 3 board is synchronous. That is, can I use the EOC (End of conversion) flag as a clock for some other modules and expect it to be a ...

fpga adc synchronous artix-series-fpga

asked Jan 17 '18 at 15:37

Sebastian Araneda

1114

0

votes

1answer

59 views

Is there an advantage to my sequential circuit optimization?

I'm trying to create a snake game on a Xilinx Artix7 FPGA, and one of the things I want to check is if the snake has collided with itself. I need to perform this check between game updates to know by ...

fpga verilog xilinx optimization artix-series-fpga

asked Dec 7 '17 at 23:17

rcplusplus

1144

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0answers

434 views

Generating Bitstream takes very long in Vivado

This question may sound very simple but the code I wrote for a seven segment display adder with pushbuttons in VHDL takes so long to generate a bitstream. I reset and tried again several times but it ...

vhdl vivado artix-series-fpga

asked Dec 4 '17 at 14:33

Ekin Alparslan

92

0

votes

1answer

95 views

SATA Connector for GTP transceivers [closed]

i have a Artix7 board with 4 SATA connector on it, i want to use these connectors for GTP transceiver, just connectors and i don't want to use SATA protocol, actually i do not know how to write XDC ...

fpga connector sata artix-series-fpga

asked Nov 24 '17 at 18:03

Foad Hoseyni

116

0

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1answer

238 views

How to implement 8b10b en/decoding protocol between two FPGAs?

I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output ...

serial decoder encoding artix-series-fpga kintex-series-fpga

asked Oct 24 '17 at 16:44

Lerbi

156

2

votes

2answers

274 views

Converting 100MHz clock to 65MHz clock for VGA

I've written some HDL code to convert the frequency of the clock on FPGA (100MHz) to a freqency which is compatible with my VGA monitor (65MHz): ...

fpga verilog hdl vga artix-series-fpga

asked Mar 25 '17 at 12:37

archity

347

0

votes

1answer

66 views

Setting up ADS1216 to use IDAC

First has anyone used this chip ADS1216 and the IDAC feature on the chip? I have tried on many occasions to get the IDAC's to work on the ADS1216 and I'm not successful. I'm using an FPGA (artix-7 w/ ...

fpga adc vhdl vivado artix-series-fpga

asked Mar 20 '17 at 16:52

hfbroady

3710

0

votes

1answer

776 views

How to use LVCMOS18 (1.8V I/O) on Artix 7 (Arty evaluation board)

I am using the ARTY 7 evaluation board from digilent which used the Artix-7 x35AT cpg324 packaging. Using one of the general purpose I/O banks i want to configure it for 1.8V configuration. (I am ...

artix-series-fpga

asked Mar 9 '17 at 23:28

CanisMajoris

2315

9

votes

1answer

615 views

Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...

xilinx routing high-speed timing-analysis artix-series-fpga

asked Aug 30 '16 at 23:55

Paebbels

3,2112933

0

votes

2answers

631 views

Sending a divided clock through a non-dedicated clock pin?

I'm moderately new to FPGA's, and right now I'm working on code to interface with a DAC. I'm using this PMOD DAC , and a Nexys 4 DDR fpga. Right now, I'm connecting them through the JB PMOD header. ...

fpga clock error peripheral artix-series-fpga

asked Aug 9 '16 at 19:08

qasddd

32

1

vote

1answer

949 views

Impedance matching on FPGA IO

I have a few questions related to impedance matching when designing a PCB board for an FPGA. I am Using Artix-7 XC7A200T-1FBG 484C. If have read this http://www.xilinx.com/support/documentation/...

impedance-matching artix-series-fpga

asked Jul 25 '16 at 6:31

Maheen

61

1

vote

0answers

870 views

VHDL: pipeline with a for loop

Question moved to: https://codereview.stackexchange.com/questions/135868/vhdl-pipeline-with-a-for-loop I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - ...

fpga vhdl zynq artix-series-fpga

asked Jul 22 '16 at 22:04

Marmoz

637

0

votes

1answer

69 views

Vivado Artix-7 Ignoring my code

I'm new to this site so excuse me if my question is not normal or a bit silly. However I am having an odd situation where Vivado 2015.4 seems to be optimizing my code and removing parts of it which it ...

fpga vivado artix-series-fpga

asked Mar 1 '16 at 18:02

K.Galea

11

3

votes

1answer

349 views

Xilinx FPGA, error creating generated clock

I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing ...

fpga verilog xilinx artix-series-fpga

asked Dec 24 '15 at 14:23

chasep255

300413

1

vote

1answer

2k views

Artix 7 Block RAM instantiation in Vivado 2015.2

Ok I'm trying to create a Block RAM instantiation in true dual port type. I have used the IP catalog and block memory generator in Vivado, which has given me a giant file that I now need to strip down ...

vhdl xilinx ram vivado artix-series-fpga

asked Dec 18 '15 at 0:04

hfbroady

3710

3

votes

1answer

3k views

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...

vhdl xilinx vivado artix-series-fpga

asked May 7 '15 at 3:49

kathir

1612

0

votes

1answer

1k views

Artix - 7 Voltage Specification I/O standard

I want to design a PCB for FPGA prototyping. Please help me understand if I need to supply these voltages and why? Vref Vrefp Vin These voltages are from the Artix-7 Datasheet. http://www.xilinx....

voltage fpga artix-series-fpga

asked Mar 25 '15 at 12:41

Shawn Mathew Kailath

114

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Questions tagged [artix-series-fpga]

How to increase memory on the FPGA board?

Vivado : constraints setup for SPI interface with common clock

single port 32x32 synchronous ram design using verilog in vivado hls

Debounce on Nexys4 DDR button

Is XADC synchronous in Artix 7 Series FPGA?

Is there an advantage to my sequential circuit optimization?

Generating Bitstream takes very long in Vivado

SATA Connector for GTP transceivers [closed]

How to implement 8b10b en/decoding protocol between two FPGAs?

Converting 100MHz clock to 65MHz clock for VGA

Setting up ADS1216 to use IDAC

How to use LVCMOS18 (1.8V I/O) on Artix 7 (Arty evaluation board)

Is my FPGA out of routing resources?

Sending a divided clock through a non-dedicated clock pin?

Impedance matching on FPGA IO

VHDL: pipeline with a for loop

Vivado Artix-7 Ignoring my code

Xilinx FPGA, error creating generated clock

Artix 7 Block RAM instantiation in Vivado 2015.2

How to solve routing issues in Artix7?

Artix - 7 Voltage Specification I/O standard

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