Questions tagged [artix-series-fpga]

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How to set a testbench file as top level entity ? [Vivado, Basys3Artix7]

This is the first time I use Vivado. I can't set test_mySWLED.v as Top I Run Behavioral Simulation End up with mySWLED waveform instead of test_mySWLED waveform. Here is my project: https://...
South goodman's user avatar
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Can I drive LVCMOS12 on Xilinx Artix-7 at 100 Mbps?

I'm currently planning a setup as shown below, where I need to operate the GPIO on my chip at a data rate of 100 Mbps. My biggest concern is whether it is a feasible to drive LVCMOS12 on Xilinx Artix-...
Emm386's user avatar
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Artix-7 SATA implementation using LiteSATA won't initialize

I am trying to run the LiteSATA bench file provided for the Nexys Video (Artix-7 xc7a200t-sbg484-1). The board is new and does not have anything connected to it, and I am building / loading the ...
md-raz's user avatar
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2 answers
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Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?

What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel. At first I was thinking of configuring on-board DDR ...
zzzhhh's user avatar
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Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?

There are 256MB DDR3L SDRAM installed on Digilent Arty A7 FPGA development board. Dual Channel memory is popular nowadays in a PC. So I was wondering if there is any chance to configure the DDR3L ...
zzzhhh's user avatar
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FPGA SPI controller ADC + posedge/negedge constraints

I want to implement the SPI controller for an ADC and have the following timing diagram : I'm implemented an FPGA controller that works on posedge clock, detecting the data coming from DOUT pin (it ...
Jorge Johanny Sáenz Noval's user avatar
2 votes
1 answer
173 views

Nexys 7 FPGA Verilog VGA signal recognized but nothing displayed

I am trying to generate images on a Samsung S22C300H monitor using the Diligent Nexys 7 board running the Xilinx Artix 7 FPGA. Even though the datasheet says the display supports 640x480, I was only ...
Luminous_'s user avatar
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How to visualize the waveform of multiple clock domain-based signals in the vio and ila?

I am a newbie to FPGA development. Any help will be highly appreciated and please forgive me in advance if the question is too obvious. The board is Chipwhisperer 305 artix-7 fpga. Used tool vivado ...
Tan007's user avatar
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1 answer
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How to get the voltage or temperature within FPGA?

I am trying to test the reliability of a circuit design on my FPGA board. (using Vivado, Artix-7 xc7a35tcsg-c board). The reliability here means the outputs of my circuit are expected to be persistent ...
Li Gaoxiang's user avatar
5 votes
2 answers
610 views

FPGA logic threshold - distinguishing a logic 0 and 1

I'm new to FPGAs and I'm trying to determine how an FPGA determines whether to register an input as a logic 0 or 1. The FPGA I am using is the Artix 7 and I would like to connect it to a function ...
PrematureCorn's user avatar
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Data transfer FPGA To PC via UART

I have implemented a TDC and an 8-bit encoder in my Artix-7 FPGA board and I want to transfer this data from FPGA to PC via UART protocol! I don't know if I should save this data in FIFO memory or ...
usereyi's user avatar
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0 answers
146 views

Daisy chaining NOR flash modules

for a project (FPGA image processing accelerator) I need to create a high bandwidth read-only memory. I settled on using Quad SPI NOR flash modules (will use them in XIP mode) but I have some concerns....
OM222O's user avatar
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What is the preferred way to store per device MAC and static IP on a Xilinx FPGA?

I've been writing some Ethernet handling code for Artix-7 FPGAs. As I said in the question I want to, on per device basis, store a device MAC and device IP address. In other words I would like to be ...
James Matta's user avatar
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Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?

The generated pinout does not list any VRP or VRN pins, or anything similar. I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
EquipDev's user avatar
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Digital Clock Manager FPGA

I want to maintain a constant frequency of 50MHz for my Nexys A7 FPGA Board. Currently, the internal clock is 100MHz. How can I implement a digital clock manager in VHDL/Verilog to make sure my ...
div_01's user avatar
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Can you share resources about implementing I2C device on FPGA? [closed]

I am using Xilinx 7 Series and the official toolchain. So far, I have been using a few Zynqs with moderate success but they come with ARM cores I don't use so I am attempting to move to a pure Artix. ...
MaxDZ8's user avatar
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BGA Stuff, unstuff PCB Pad Short

I am using Artix 7 FPGA (XC7A200T-2FPG676) BGA package on PCB, after unstuffing of FPGA I want to short two pad P18 and R18 on PCB with each other and then wants to stuff back my FPGA . Note: P18 and ...
Sardar Awais Gujjar's user avatar
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Shorter transmission lines or nearer high frequency bypass caps

I have an application where I have a sensor which communicates with an FPGA with about 15 differential pairs of data clocking around 300 Mhz. Due to constraints, the board can't be taller than 35mm ...
Joshua's user avatar
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Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated. When looking at the reference manual of the Arty7 board, I see that I have to ...
GNA's user avatar
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1 vote
1 answer
462 views

How to improve timing on this design using so much BlockRAM?

I'm building a small RISC FPGA CPU on an Artix-7 (Arty A7-100 (xc7a100tcsg324-1) board. It runs fine, most instructions take three clocks (non-pipelined), but due to crazy net delays, can only run at ...
TomServo's user avatar
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1 answer
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Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...
jrive's user avatar
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24-bit binary to 32-bit bcd

I'm trying to write a 24bin-32bcd BCD counter. Can anyone explain how to implement it ? Here is my code: http://tpcg.io/JOHf4IFj but it needs to be checked. I have some problems with "valid" ...
L.Kh.Hovhannisyan's user avatar
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2 answers
1k views

Basys 3 400MHz Logic [duplicate]

The Basys 3 advertises "internal clock speeds exceeding 450 MHz," but the default clock pin is connected to a 100MHz oscillator. Is it possible to configure the Basys 3 to use a 450MHz clock?
Astrid Yu's user avatar
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How do Vivado and Vitis determine where stack and heap are located?

Been taking advantage of lockdown to learn how to work with softcores and C on Vivado/Vitis, using a Digilent CMOD A7 board I have. I managed to get the out of box demo built and running, but I hit a ...
danmcb's user avatar
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1 answer
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Can an incorrect VGA timing kill a modern LCD screen?

I'm going to play with an Artix-7 dev board with a VGA port (Nexys 4 DDR from Digilent) and I'm a beginner at this. Assuming the pinout is correct, is it possible to destroy a (very) cheap modern LCD ...
ker2x's user avatar
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1 answer
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External CLK in Artix-7

I try to design a board with an ARTIX-7 FPGA. There is a big question that which pin of FPGA should I put an oscillator? I inspected a document about clocking the 7 series xilinx FPGA (7 Series FPGAs ...
parisa-far's user avatar
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Zynq 7020 subcomponent equivalent parts [closed]

The Xiling Zynq 7020 has a dual-core ARM Cortex-A9 and an Artix-7 FPGA in it. What is the equivalent part number of these chips independently? (i.e. what individual part numbers have the same ...
iAdjunct's user avatar
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1 answer
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How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
IgNite's user avatar
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3 votes
1 answer
2k views

Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...
CanisMajoris's user avatar
3 votes
2 answers
773 views

Debounce on Nexys4 DDR button

I am trying to implement a simple UART transmitter, where the Nexys4 DDR board is sending ASCII characters to my PC, which I can view using Tera Term. The problem I am having is that when I press one ...
nnja's user avatar
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2 votes
1 answer
334 views

Is XADC synchronous in Artix 7 Series FPGA?

I was wondering if the output data of the XADC in the Basys 3 board is synchronous. That is, can I use the EOC (End of conversion) flag as a clock for some other modules and expect it to be a ...
Sebastian Araneda's user avatar
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1 answer
74 views

Is there an advantage to my sequential circuit optimization?

I'm trying to create a snake game on a Xilinx Artix7 FPGA, and one of the things I want to check is if the snake has collided with itself. I need to perform this check between game updates to know by ...
rcplusplus's user avatar
2 votes
0 answers
2k views

Generating Bitstream takes very long in Vivado

This question may sound very simple but the code I wrote for a seven segment display adder with pushbuttons in VHDL takes so long to generate a bitstream. I reset and tried again several times but it ...
Ekin Alparslan's user avatar
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1 answer
202 views

SATA Connector for GTP transceivers [closed]

i have a Artix7 board with 4 SATA connector on it, i want to use these connectors for GTP transceiver, just connectors and i don't want to use SATA protocol, actually i do not know how to write XDC ...
Foad Hoseyni's user avatar
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1 answer
2k views

How to implement 8b10b en/decoding protocol between two FPGAs?

I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output ...
Lerbi's user avatar
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1 vote
2 answers
665 views

Converting 100MHz clock to 65MHz clock for VGA

I've written some HDL code to convert the frequency of the clock on FPGA (100MHz) to a freqency which is compatible with my VGA monitor (65MHz): ...
archity's user avatar
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1 answer
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Setting up ADS1216 to use IDAC

First has anyone used this chip ADS1216 and the IDAC feature on the chip? I have tried on many occasions to get the IDAC's to work on the ADS1216 and I'm not successful. I'm using an FPGA (artix-7 w/ ...
hfbroady's user avatar
1 vote
1 answer
3k views

How to use LVCMOS18 (1.8V I/O) on Artix 7 (Arty evaluation board)

I am using the ARTY 7 evaluation board from digilent which used the Artix-7 x35AT cpg324 packaging. Using one of the general purpose I/O banks i want to configure it for 1.8V configuration. (I am ...
CanisMajoris's user avatar
9 votes
1 answer
1k views

Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...
Paebbels's user avatar
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0 votes
2 answers
1k views

Sending a divided clock through a non-dedicated clock pin?

I'm moderately new to FPGA's, and right now I'm working on code to interface with a DAC. I'm using this PMOD DAC , and a Nexys 4 DDR fpga. Right now, I'm connecting them through the JB PMOD header. ...
qasddd's user avatar
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1 vote
1 answer
3k views

Impedance matching on FPGA IO

I have a few questions related to impedance matching when designing a PCB board for an FPGA. I am Using Artix-7 XC7A200T-1FBG 484C. If have read this http://www.xilinx.com/support/documentation/...
Maheen's user avatar
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0 answers
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VHDL: pipeline with a for loop

Question moved to: https://codereview.stackexchange.com/questions/135868/vhdl-pipeline-with-a-for-loop I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - ...
Marmoz's user avatar
  • 336
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1 answer
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Vivado Artix-7 Ignoring my code

I'm new to this site so excuse me if my question is not normal or a bit silly. However I am having an odd situation where Vivado 2015.4 seems to be optimizing my code and removing parts of it which it ...
K.Galea's user avatar
4 votes
1 answer
741 views

Xilinx FPGA, error creating generated clock

I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing ...
chasep255's user avatar
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1 vote
1 answer
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Artix 7 Block RAM instantiation in Vivado 2015.2

Ok I'm trying to create a Block RAM instantiation in true dual port type. I have used the IP catalog and block memory generator in Vivado, which has given me a giant file that I now need to strip down ...
hfbroady's user avatar
3 votes
1 answer
4k views

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...
kathir's user avatar
  • 31
0 votes
1 answer
3k views

Artix - 7 Voltage Specification I/O standard

I want to design a PCB for FPGA prototyping. Please help me understand if I need to supply these voltages and why? Vref Vrefp Vin These voltages are from the Artix-7 Datasheet. http://www.xilinx....
Shawn Mathew Kailath's user avatar