Newest 'artix-series-fpga' Questions

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Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated. When looking at the reference manual of the Arty7 board, I see that I have to ...

asked Dec 31 '20 at 19:54

GNA

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FPGA design xilinx

The ASMBL architecture breaks through traditional design barriers by: Eliminating geometric layout constraints such as dependencies between I/O count and array size. Enhancing on-chip power and ...

fpga artix-series-fpga

asked Dec 26 '20 at 8:47

Tech Visionary

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CMOD A7 Seeing Input Even When There is None

I've created a quantum-random number generator which is outputting random pulses to 8 IO pins on my FPGA. I've implemented the following input component to lengthen the ~10ns pulses to something my ...

fpga vhdl artix-series-fpga

asked Dec 6 '20 at 16:18

Persistence

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How to improve timing on this design using so much BlockRAM?

I'm building a small RISC FPGA CPU on an Artix-7 (Arty A7-100 (xc7a100tcsg324-1) board. It runs fine, most instructions take three clocks (non-pipelined), but due to crazy net delays, can only run at ...

fpga verilog xilinx artix-series-fpga

asked Dec 3 '20 at 23:29

TomServo

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Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...

vivado timing-analysis constraints artix-series-fpga

asked Oct 28 '20 at 15:07

jrive

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24-bit binary to 32-bit bcd

I'm trying to write a 24bin-32bcd BCD counter. Can anyone explain how to implement it ? Here is my code: http://tpcg.io/JOHf4IFj but it needs to be checked. I have some problems with "valid" ...

microcontroller fpga verilog artix-series-fpga microsemi-fpga

asked Aug 22 '20 at 6:50

L.Kh.Hovhannisyan

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Read/write Artix RTL registers at runtime from UART interface

I have an RTL design on an Arty board that is composed of clock managers and counters. The counters have individual enables and wraparound values (all hardcoded). I want to enhance it to write ...

uart vivado artix-series-fpga microblaze xilinx-sdk

asked Jul 14 '20 at 5:23

JackOTrade

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Basys 3 400MHz Logic [duplicate]

The Basys 3 advertises "internal clock speeds exceeding 450 MHz," but the default clock pin is connected to a 100MHz oscillator. Is it possible to configure the Basys 3 to use a 450MHz clock?

fpga xilinx artix-series-fpga

asked Jun 3 '20 at 6:31

Astrid Yu

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How do Vivado and Vitis determine where stack and heap are located?

Been taking advantage of lockdown to learn how to work with softcores and C on Vivado/Vitis, using a Digilent CMOD A7 board I have. I managed to get the out of box demo built and running, but I hit a ...

c xilinx vivado artix-series-fpga vitis

asked Mar 15 '20 at 17:34

danmcb

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Can an incorrect VGA timing kill a modern LCD screen?

I'm going to play with an Artix-7 dev board with a VGA port (Nexys 4 DDR from Digilent) and I'm a beginner at this. Assuming the pinout is correct, is it possible to destroy a (very) cheap modern LCD ...

fpga vga artix-series-fpga

asked Oct 11 '19 at 9:26

ker2x

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External CLK in Artix-7

I try to design a board with an ARTIX-7 FPGA. There is a big question that which pin of FPGA should I put an oscillator? I inspected a document about clocking the 7 series xilinx FPGA (7 Series FPGAs ...

fpga clock artix-series-fpga

asked Jun 26 '19 at 8:07

parisa-far

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Zynq 7020 subcomponent equivalent parts [closed]

The Xiling Zynq 7020 has a dual-core ARM Cortex-A9 and an Artix-7 FPGA in it. What is the equivalent part number of these chips independently? (i.e. what individual part numbers have the same ...

fpga arm artix-series-fpga arm9

asked May 8 '19 at 22:05

iAdjunct

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How to increase memory on the FPGA board?

Situation I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...

fpga memory xilinx zynq artix-series-fpga

asked Feb 11 '19 at 20:47

IgNite

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Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...

fpga spi vivado constraints artix-series-fpga

asked Nov 4 '18 at 3:26

CanisMajoris

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single port 32x32 synchronous ram design using verilog in vivado hls

in the verilog code below: ...

verilog vivado zynq artix-series-fpga

asked Sep 26 '18 at 5:05

Shubham Choudhary

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471 views

Debounce on Nexys4 DDR button

I am trying to implement a simple UART transmitter, where the Nexys4 DDR board is sending ASCII characters to my PC, which I can view using Tera Term. The problem I am having is that when I press one ...

fpga vhdl artix-series-fpga

asked Jan 26 '18 at 19:29

nnja

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280 views

Is XADC synchronous in Artix 7 Series FPGA?

I was wondering if the output data of the XADC in the Basys 3 board is synchronous. That is, can I use the EOC (End of conversion) flag as a clock for some other modules and expect it to be a ...

fpga adc synchronous artix-series-fpga

asked Jan 17 '18 at 15:37

Sebastian Araneda

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Is there an advantage to my sequential circuit optimization?

I'm trying to create a snake game on a Xilinx Artix7 FPGA, and one of the things I want to check is if the snake has collided with itself. I need to perform this check between game updates to know by ...

fpga verilog xilinx optimization artix-series-fpga

asked Dec 7 '17 at 23:17

rcplusplus

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Generating Bitstream takes very long in Vivado

This question may sound very simple but the code I wrote for a seven segment display adder with pushbuttons in VHDL takes so long to generate a bitstream. I reset and tried again several times but it ...

vhdl vivado artix-series-fpga

asked Dec 4 '17 at 14:33

Ekin Alparslan

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151 views

SATA Connector for GTP transceivers [closed]

i have a Artix7 board with 4 SATA connector on it, i want to use these connectors for GTP transceiver, just connectors and i don't want to use SATA protocol, actually i do not know how to write XDC ...

fpga connector sata artix-series-fpga

asked Nov 24 '17 at 18:03

Foad Hoseyni

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How to implement 8b10b en/decoding protocol between two FPGAs?

I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output ...

serial decoder encoding artix-series-fpga kintex-series-fpga

asked Oct 24 '17 at 16:44

Lerbi

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448 views

Converting 100MHz clock to 65MHz clock for VGA

I've written some HDL code to convert the frequency of the clock on FPGA (100MHz) to a freqency which is compatible with my VGA monitor (65MHz): ...

fpga verilog hdl vga artix-series-fpga

asked Mar 25 '17 at 12:37

archity

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112 views

Setting up ADS1216 to use IDAC

First has anyone used this chip ADS1216 and the IDAC feature on the chip? I have tried on many occasions to get the IDAC's to work on the ADS1216 and I'm not successful. I'm using an FPGA (artix-7 w/ ...

fpga adc vhdl vivado artix-series-fpga

asked Mar 20 '17 at 16:52

hfbroady

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How to use LVCMOS18 (1.8V I/O) on Artix 7 (Arty evaluation board)

I am using the ARTY 7 evaluation board from digilent which used the Artix-7 x35AT cpg324 packaging. Using one of the general purpose I/O banks i want to configure it for 1.8V configuration. (I am ...

artix-series-fpga

asked Mar 9 '17 at 23:28

CanisMajoris

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Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...

xilinx routing high-speed timing-analysis artix-series-fpga

asked Aug 30 '16 at 23:55

Paebbels

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2answers

832 views

Sending a divided clock through a non-dedicated clock pin?

I'm moderately new to FPGA's, and right now I'm working on code to interface with a DAC. I'm using this PMOD DAC , and a Nexys 4 DDR fpga. Right now, I'm connecting them through the JB PMOD header. ...

fpga clock error peripheral artix-series-fpga

asked Aug 9 '16 at 19:08

qasddd

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Impedance matching on FPGA IO

I have a few questions related to impedance matching when designing a PCB board for an FPGA. I am Using Artix-7 XC7A200T-1FBG 484C. If have read this http://www.xilinx.com/support/documentation/...

impedance-matching artix-series-fpga

asked Jul 25 '16 at 6:31

Maheen

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VHDL: pipeline with a for loop

Question moved to: https://codereview.stackexchange.com/questions/135868/vhdl-pipeline-with-a-for-loop I'm implementing an AXI4-Stream module. The module uses three DSP blocks (DSP49E1, UG479 - ...

fpga vhdl zynq artix-series-fpga

asked Jul 22 '16 at 22:04

Marmoz

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Vivado Artix-7 Ignoring my code

I'm new to this site so excuse me if my question is not normal or a bit silly. However I am having an odd situation where Vivado 2015.4 seems to be optimizing my code and removing parts of it which it ...

fpga vivado artix-series-fpga

asked Mar 1 '16 at 18:02

K.Galea

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votes

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466 views

Xilinx FPGA, error creating generated clock

I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing ...

fpga verilog xilinx artix-series-fpga

asked Dec 24 '15 at 14:23

chasep255

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Artix 7 Block RAM instantiation in Vivado 2015.2

Ok I'm trying to create a Block RAM instantiation in true dual port type. I have used the IP catalog and block memory generator in Vivado, which has given me a giant file that I now need to strip down ...

vhdl xilinx ram vivado artix-series-fpga

asked Dec 18 '15 at 0:04

hfbroady

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How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub ...

vhdl xilinx vivado artix-series-fpga

asked May 7 '15 at 3:49

kathir

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Artix - 7 Voltage Specification I/O standard

I want to design a PCB for FPGA prototyping. Please help me understand if I need to supply these voltages and why? Vref Vrefp Vin These voltages are from the Artix-7 Datasheet. http://www.xilinx....

voltage fpga artix-series-fpga

asked Mar 25 '15 at 12:41

Shawn Mathew Kailath

114 bronze badges

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Questions tagged [artix-series-fpga]

Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

FPGA design xilinx

CMOD A7 Seeing Input Even When There is None

How to improve timing on this design using so much BlockRAM?

Passing input on one pin of FPGA straight out to another output pin for monitoring

24-bit binary to 32-bit bcd

Read/write Artix RTL registers at runtime from UART interface

Basys 3 400MHz Logic [duplicate]

How do Vivado and Vitis determine where stack and heap are located?

Can an incorrect VGA timing kill a modern LCD screen?

External CLK in Artix-7

Zynq 7020 subcomponent equivalent parts [closed]

How to increase memory on the FPGA board?

Vivado : constraints setup for SPI interface with common clock

single port 32x32 synchronous ram design using verilog in vivado hls

Debounce on Nexys4 DDR button

Is XADC synchronous in Artix 7 Series FPGA?

Is there an advantage to my sequential circuit optimization?

Generating Bitstream takes very long in Vivado

SATA Connector for GTP transceivers [closed]

How to implement 8b10b en/decoding protocol between two FPGAs?

Converting 100MHz clock to 65MHz clock for VGA

Setting up ADS1216 to use IDAC

How to use LVCMOS18 (1.8V I/O) on Artix 7 (Arty evaluation board)

Is my FPGA out of routing resources?

Sending a divided clock through a non-dedicated clock pin?

Impedance matching on FPGA IO

VHDL: pipeline with a for loop

Vivado Artix-7 Ignoring my code

Xilinx FPGA, error creating generated clock

Artix 7 Block RAM instantiation in Vivado 2015.2

How to solve routing issues in Artix7?

Artix - 7 Voltage Specification I/O standard

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Questions tagged [artix-series-fpga]

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