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Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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325 views

What material(s) are used in IC's as insulating layers between metal layers?

This question and the answers hits close to the topic. One picture shows it as SOD. Silicon-oxide dielectric? I'm aware that around/within the transistor, silicon oxide is grown for insulation where ...
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1answer
311 views

Is there a fieldbus with more than 250 nodes per segment?

We plan to realize a sensor cable several 1000m long which has ideally every 1-2m a magnetic field sensor on a small 10x30mm platine with microprocessor/FPGA for DSP and I2C on chip communication. ...
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131 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
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557 views

ASIC verification of a FIFO with “n” unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
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Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
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1answer
110 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
430 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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2answers
508 views

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...
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1answer
92 views

How to scale output of butterfly unit radix 2 for further stages?

I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for ...
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1answer
314 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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1answer
85 views

Designing ASIC Chip for Enterprise [closed]

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring ...
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11 views

Innovus MMMC import

I am exploring Genus and Innovus tools, I noticed to import a design in Innovus we have to import MMMC.tcl file, is this file provided or have to be generated by Genus ? or needs to be written ...
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1answer
61 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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47 views

Flipflop value a long time after startup

After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...
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78 views

Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]

If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1. But if LSB comes in first, how can we come up with ...
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1answer
184 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
68 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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29 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
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10answers
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How much does it cost to have a custom ASIC made?

I have browsed several ASIC manufacturer's webs, but I haven't found an actual number. I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
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3answers
188 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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0answers
48 views

Do Broadcom's Ethernet chipsets need special software to operate?

I want to implement an Ethernet switch using Broadcom's chips. Are singing an NDA and getting the datasheets enough to work with the chips? I have heard that the chips must be programmed by a special ...
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1answer
477 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
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How to simulate a piezoresistive pressure sensing MEMs layout without COMSOL?

I have a masks layout of a Piezoresistive MEMs pressure device that I've designed in LEdit(Tanner Tools Eda). The device consists of 4 piezoresistors bonded onto a thin diaphragm which deforms ...
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4answers
438 views

Is an ethernet switch considered as an ASIC?

I work as an electronic reliability engineer. In order to estimate the reliability of integrated circuits, I need to know their type. Thus my question. Is this ethernet switch Marvell Link Street-...
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5answers
433 views

Are there fully open-source ASICs?

The Ethereum Foundation (an open-source project) will build an open-source ASIC to support its decentralised randomness beacon. To date, has the RTL of any ASIC been open-sourced or will the Ethereum ...
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TSMC's 16nm FF+ “GL” and “LL” variants

TSMC has GL and LL variants for their 16nm FinFET plus process. (For example, see here.) What do GL and LL stand for? Is there publicly available information about the differences between these two ...
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2answers
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How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
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5answers
46k views

What are the differences and similarities between FPGA, ASIC and General Microcontrollers?

I have read this post and it does not answer my question in its entirety: I think of a microcontroller as anything that has some memory, registers, and can process a set of instructions such as LOAD, ...
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5answers
1k views

Is it good practice to always assign initial value and reset signals in digital design?

I have read that initial values to a signal can be set in an FPGA since the design is "loaded into it" after power up. However, in ASICs we can only rely on a reset signal to put all signals into a ...
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2answers
284 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
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202 views

Beyond liquid helium cooling

Liquid helium has a boiling point of around -269°C and is used by overclockers. It has led to various world records (e.g. see here and here). What cooling technology can beat liquid helium for the ...
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201 views

Gate and routing delays as a function of voltage and temperature

As I understand from watching overclocking videos, the maximum operating frequency of a digital ASIC is a function of voltage and temperature. Specifically, it seems that the maximum operating ...
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2answers
47 views

Maximum power draw density of digital ASIC

Given a process node (e.g. TSMC's 16nm FinFET+) what is the maximum power per mm2 that a digital ASIC can draw? Secondary question: Assuming liquid nitrogen cooling, what would be the bottleneck ...
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37 views

How can I access process node data sheets?

I am searching for process node data sheets. Specifically, I'm interested in TSMC's 16nm, 12nm, 10nm, 7nm nodes, as well as Samsung's 14nm, 10nm nodes. I did not find anything with Google. How can I ...
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4answers
628 views

Exotic semiconductors for fast digital ASIC

I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-...
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2answers
10k views

Understanding combinational feedback loops

Please give me a simple example of a verilog code that results in combo feedback loop. Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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2answers
48 views

What is meant by process “performance”?

I am reading the product page for TSMC's 20nm process. It states Compared to its 28nm node, the 20nm process provides 15% better performance and can reduce total power consumption by a third. What ...
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1answer
175 views

Large SiGe ASICs for digital logic

I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a ...
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1answer
97 views

65nm silicon-germanium

The Wikipedia page on silicon-germanium states that AMD and IBM worked on a 65nm SiGe process. Unfortunately the source is no longer up and I cannot find more information about the 65nm SiGe process. ...
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1answer
372 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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1answer
68 views

How to find a design house with dynamic memory device support? [closed]

I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...
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108 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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83 views

Gated integrator IC, non continuous

Can anyone give me any suggestions for some good gated voltage integrators that aren't continuous, and more like a boxcar integrator? I want to integrate the the total voltage across a pulse coming ...
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2answers
332 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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2answers
103 views

Mixing reset and non reset registers

If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way... ...
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2answers
269 views

Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
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3answers
889 views

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
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What are Soft, Firm and Hard IP Cores? [closed]

My understanding of Intellectual Property (IP) Cores is that they are specific FPGA or ASIC circuit layouts or setups with the intention of being sold for general use. What are Soft, Firm and Hard IP ...
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1answer
110 views

Can we connect both ASIC and an FPGA both to the same physical output Ethernet ports at the same time? [closed]

I am doing simulation of my research design on single FPGA, in which I simulated two switching chips ASIC and an FPGA. I mean, I simulated single FPGA working as two chips, and connected them so that ...
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1answer
311 views

VHDL: Optmize signal comparisons for synthesis

As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...