Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

Filter by
Sorted by
Tagged with
0
votes
1answer
555 views

ASIC verification of a FIFO with “n” unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
9
votes
4answers
2k views

Can you get a Passive ASIC?

In super small low power devices, where space is a big premium, complicated passive networks can take up a lot of space. Is it possible to get a passive or mostly passive ASIC fabricated? If it is ...
1
vote
1answer
98 views

Can I order PCB/chip manufacture from provided LOTOS specification?

Is there a way to automatically deduct PCB and/or chip design from formal problem specification of a problem (task) which supposed to be solved on a PCB/chip? I'm currently implementing solution with ...
1
vote
2answers
268 views

Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
0
votes
2answers
103 views

Mixing reset and non reset registers

If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way... ...
1
vote
2answers
1k views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
-5
votes
1answer
136 views

Whats the difference between an FPGA and an ASIC [closed]

I know what an FPGA and ASIC are. However what I want to know is what is the difference with cost and time. How long does it take to build an FPGA? How long does it take to build an ASIC? How much ...
0
votes
1answer
122 views

Which fab for DRAM device? (ASIC design at Europractice)

I would like to ask for advice. Europractice supports many fabs and technologies for custom asic design (fab list). Lib support list of those technologies are public (for example UMC 130 nm LL). I ...
2
votes
2answers
302 views

Can multi-project wafer service merge projects with different number of layers?

I would like to ask some help to better understand limitations of multi-project wafer services (MPW). In nutshell, i found about the service, that it merges many projects on wafer, so one project ...
0
votes
1answer
579 views

Connect PCIe x1 port to an ASIC PCIe x4 [closed]

I want to connect a microcontroller with a PCIe x1 port to an ASIC with PCIe x4 interface. It is not possible to connect microcontroller to lane 0 of ASIC, and it should be connected to other lanes (...
0
votes
0answers
78 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
0
votes
2answers
634 views

How does asynchronous and synchronous reset signal affect the setup and hold time in a Flip Flop?

Does the async. and sync. reset signal follow the setup and hold time conditions of flip flop? If so how would they affect the output?
1
vote
4answers
194 views

Is there an “additive manufacturing” method to make an ASIC?

Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting ...
2
votes
2answers
164 views

How is the bias current reference value determined for CMOS circuit design?

In the few textbooks I'm reading on CMOS analog design, they all seem to have reference currents of \$10 \mu A\$ or similar that get mirrored, and there doesn't seem to be any discussion on how this ...
6
votes
1answer
477 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
1
vote
1answer
207 views

Is RAM with read ahead (Look ahead) possible?

Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports? A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
3
votes
2answers
2k views

Clock Domain Crossing for Pulse and Level Signal

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that? EDIT: After @...
3
votes
1answer
484 views

Power categories in ASIC design (Design Compiler)

I am currently working on the synthesis, with Synopsys' Design Compiler, of an AES encryption module. In the power reports there are three power categories specified : Switching Power Internal Power ...
0
votes
1answer
148 views

Baseband Processor

If a device can only be activated by way of RF then I would tend to believe that the BB processor (embedded via ASIC design) would need to be active and powered on yes ? If correct then does it have ...
0
votes
1answer
182 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
0
votes
2answers
113 views

How does a device that is RF enabled power up the main CPU by way of RF?

Suppose you have a device such as a wireless video camera and the only way to power on the device is by way of RF. If the video camera has a CPU how can the baseband IC power up this CPU ? Is it ...
-5
votes
2answers
10k views

Chip vs printed circuit board [closed]

What is the difference between a chip, wafer, and PCB? Are PCB individual components cut out from bigger wafers?
1
vote
4answers
6k views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
2
votes
1answer
344 views

how do you know the each parameter values of SDC at the first time?

when we do synthesis with SDC. we should be used with SDC. But I want to know what if you are in situation where the synthesis of yours is the first time, also the company does not even did synthesis ...
0
votes
1answer
410 views

Are there any alternatives to ASIC chips? [closed]

Are there any other mixed-signal integrated circuit embedded systems (or alternative solutions) which are faster than ASIC in terms of performance (let say for a high-efficiency Bitcoin miner)?
3
votes
1answer
1k views

Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
0
votes
1answer
214 views

Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me: 1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
0
votes
1answer
839 views

How is the difference between sdf back annotation and spf back annotation?

I'm a rtl engineer. I'm confused between the difference of sdf and spf back annotation. As I know sdf came from STA( PT) and SPF came from STAR-RC. So In my experiance, the sdf used to timing close ...
-4
votes
1answer
232 views

How can we use D flip flop and a combinational circuit to retain a bit?

I am trying to solve a problem, which involves designing a gate level circuit, and I'm stuck on the last part of the problem. The last part wants me to retain the carry flag generated from the adder ...
0
votes
2answers
3k views

How to find high fanout nets?

In the timing report of a synthesis with Synopsys VCS, a warning states: Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
0
votes
1answer
88 views

data bus power consumption

In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing: use a mux for the read data of each master, so that if the ...
0
votes
1answer
301 views

ASIC Power supply requirements

I am a newbie in ASIC design process and have a question. What is difference (or pros and cons) of shorting the voltage supply pins(which have the same voltage requirements) in package level or in die(...
5
votes
3answers
2k views

Is it possible to “crack” an ASIC?

Could someone break an ASIC? If an ASIC is a fully customized, app-specific CPU, is possible to reverse engineer it? I'd imagine the answer in general is no, since to me the only way to do this ...
1
vote
1answer
389 views

What runs a g-shock watch?

I am currently trying to learn more about watches and what it takes to build them. I currently own a watch called the G-Shock 7900b and was wondering what runs it inside. Here is a link to the watch: ...
1
vote
1answer
122 views

Is there an easy way to physically implement a simple digital circuit?

I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
2
votes
1answer
2k views

Setup and Hold time VS temperature (and temperature inversion)

So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is ...
25
votes
5answers
46k views

What are the differences and similarities between FPGA, ASIC and General Microcontrollers?

I have read this post and it does not answer my question in its entirety: I think of a microcontroller as anything that has some memory, registers, and can process a set of instructions such as LOAD, ...
1
vote
2answers
334 views

ASIC fabrication companies [closed]

What is the cheapest way to synthesize ASICs in small quantities? (5-10 chips). I'm asking for a specific company, not method.
0
votes
2answers
10k views

Understanding combinational feedback loops

Please give me a simple example of a verilog code that results in combo feedback loop. Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
1
vote
1answer
5k views

Understanding (PVT) Corners

1) Do corners always refer to PVT corners in ASIC design? Or are there any other elements involved in a corner? 2) On what basis are corners named "Slow", "Typical" & "Fast"? 3) What factors ...
8
votes
3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
5
votes
1answer
939 views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
2
votes
2answers
3k views

How to obtain the (estimate) equivalent gate count for a FPGA design?

I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by ...
0
votes
2answers
117 views

Power analysis after placement and routing of ASIC

How can I procure the files stating the details of power consumption of the chip after PNR in SOC Cadence Encounter?
2
votes
1answer
202 views

Computational complexity of current netlist matching algorithms

I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
0
votes
2answers
235 views

Cadence SoC encounter

I am trying to create the layout of my design for an 8 bit multiplier accumulator in SoC Cadence encounter tool. After routing the design using wroute command, the ...
2
votes
2answers
1k views

How fast can a modern ASIC be clocked?

Modern CPUs today are commonly clocked in the 3-4 GHz range. How fast can typical modern ASICs be clocked? For example if I were building a commodity ASIC for something like a disk drive or ...
0
votes
2answers
198 views

How do the three wires for each HDMI Channel relate to a single signal?

I'm working on an HDMI ASIC and the HDMI spec is very clear on everything except for the way that the +, -, and shield wires are used to transmit a given signal. The TDMS channels and the clock are ...
1
vote
2answers
567 views

Flash Memory on an ASIC

Are flash memory and ROM also considered integrated circuits? And so, is it possible to embed a flash memory or a ROM into an ASIC?
0
votes
4answers
2k views

In CMOS, can I assume the delay of a multiplexer is negligible compared to the delay of an inverter?

Let say I have a ring oscillator, and I modify the ring so that the output of an inverter is connected to an input of a 2-to-1 MUX, and the output of the MUX is connected to the input of the next ...