Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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10answers
84k views

How much does it cost to have a custom ASIC made?

I have browsed several ASIC manufacturer's webs, but I haven't found an actual number. I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
42
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2answers
12k views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
14
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5answers
12k views

Reset: synchronous vs asynchronous

I've been working with fpgas for years, and always used synchronous resets for every parts (that need it) of my circuits. It helps the circuit to be globally reset at a given clock cycle. However, I ...
7
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4answers
622 views

Exotic semiconductors for fast digital ASIC

I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-...
2
votes
3answers
1k views

What are the general steps used in creating a ASIC?

I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered Once a logic design is tested on an FPGA it ...
17
votes
5answers
10k views

What are the practical uses of ASIC?

Microcontrollers, FPGAs, ASIC (Application-specific integrated circuit) all are used for similar type of applications (at different levels). I know about microcontrollers and FPGAs. But what is an ...
8
votes
3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
3
votes
1answer
1k views

Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
4
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3answers
2k views

Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process

I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and ...
4
votes
2answers
747 views

ASIC Shuttle Service Disadvantages?

Im trying to learn a bit about the techniques to create an ASIC. I found that the NRE-Costs are the biggest cost part which means the creationg of the masks and you get a minimum number of ASICs back. ...
2
votes
2answers
294 views

Can multi-project wafer service merge projects with different number of layers?

I would like to ask some help to better understand limitations of multi-project wafer services (MPW). In nutshell, i found about the service, that it merges many projects on wafer, so one project ...