Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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84 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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304 views

Is there a fieldbus with more than 250 nodes per segment?

We plan to realize a sensor cable several 1000m long which has ideally every 1-2m a magnetic field sensor on a small 10x30mm platine with microprocessor/FPGA for DSP and I2C on chip communication. ...
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407 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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344 views

Area vs Operating Frequency in asic synthesis

I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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111 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
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11 views

Innovus MMMC import

I am exploring Genus and Innovus tools, I noticed to import a design in Innovus we have to import MMMC.tcl file, is this file provided or have to be generated by Genus ? or needs to be written ...
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46 views

Flipflop value a long time after startup

After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...
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28 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
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47 views

Do Broadcom's Ethernet chipsets need special software to operate?

I want to implement an Ethernet switch using Broadcom's chips. Are singing an NDA and getting the datasheets enough to work with the chips? I have heard that the chips must be programmed by a special ...
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41 views

How to simulate a piezoresistive pressure sensing MEMs layout without COMSOL?

I have a masks layout of a Piezoresistive MEMs pressure device that I've designed in LEdit(Tanner Tools Eda). The device consists of 4 piezoresistors bonded onto a thin diaphragm which deforms ...
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52 views

TSMC's 16nm FF+ “GL” and “LL” variants

TSMC has GL and LL variants for their 16nm FinFET plus process. (For example, see here.) What do GL and LL stand for? Is there publicly available information about the differences between these two ...
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37 views

How can I access process node data sheets?

I am searching for process node data sheets. Specifically, I'm interested in TSMC's 16nm, 12nm, 10nm, 7nm nodes, as well as Samsung's 14nm, 10nm nodes. I did not find anything with Google. How can I ...
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94 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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80 views

Gated integrator IC, non continuous

Can anyone give me any suggestions for some good gated voltage integrators that aren't continuous, and more like a boxcar integrator? I want to integrate the the total voltage across a pulse coming ...
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92 views

How to scale output of butterfly unit radix 2 for further stages?

I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for ...
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109 views

How to measure dynamic power consumption of each component of a Microcontroller?

I am interested to get the dynamic power consumption of each of the component of a micro-controller. Can I do it by adding the power lines in place and route (PAR)? The purpose of it to get the more ...
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524 views

ASIC verification of a FIFO with “n” unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
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72 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...