Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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155
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10answers
84k views

How much does it cost to have a custom ASIC made?

I have browsed several ASIC manufacturer's webs, but I haven't found an actual number. I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
42
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2answers
12k views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
24
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5answers
45k views

What are the differences and similarities between FPGA, ASIC and General Microcontrollers?

I have read this post and it does not answer my question in its entirety: I think of a microcontroller as anything that has some memory, registers, and can process a set of instructions such as LOAD, ...
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5answers
10k views

What are the practical uses of ASIC?

Microcontrollers, FPGAs, ASIC (Application-specific integrated circuit) all are used for similar type of applications (at different levels). I know about microcontrollers and FPGAs. But what is an ...
14
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5answers
12k views

Reset: synchronous vs asynchronous

I've been working with fpgas for years, and always used synchronous resets for every parts (that need it) of my circuits. It helps the circuit to be globally reset at a given clock cycle. However, I ...
12
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1answer
1k views

What are Soft, Firm and Hard IP Cores? [closed]

My understanding of Intellectual Property (IP) Cores is that they are specific FPGA or ASIC circuit layouts or setups with the intention of being sold for general use. What are Soft, Firm and Hard IP ...
9
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4answers
2k views

Can you get a Passive ASIC?

In super small low power devices, where space is a big premium, complicated passive networks can take up a lot of space. Is it possible to get a passive or mostly passive ASIC fabricated? If it is ...
9
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6answers
5k views

How does program execution happen in firmware?

I have heard from people working in firmware domain, that there is no Operating system controlling firmware (eg firmware in a USB drive). There is just a single thread running in a while loop waiting ...
8
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3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
7
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2answers
484 views

ASIC Verfication Do I need to verify all possible combinations?

I'm currently doing ASIC Black box Verification. Suppose I got a module with 200 input ports with 12 bit width each and a one output port with 64 bit width. Lets say, its pure combinational inside. <...
7
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4answers
620 views

Exotic semiconductors for fast digital ASIC

I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-...
7
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3answers
649 views

What can go wrong when producing an ASIC from an FPGA-verified verilog design?

Given a Verilog design fully validated on an FPGA prototyping system, and someone who has never done an ASIC before, what are the chances that a service like CMP will ship fully usable chips on the ...
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3answers
3k views

ASIC vs ? — Performance & Cost

I'm interested in creating a custom linux based solution that will crunch sha256 cryptographic algorithms at insane levels of speed. I'm also on a limited budget... I have no background in EE but I ...
6
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3answers
662 views

Why do embedded systems need to be programmable?

According to my understanding, certain types of embedded systems are dedicated to a particular task. Why, then, do engineers not transfer all the burden of processing onto the hardware in the form of ...
6
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4answers
4k views

Getting starting designing CMOS ASIC - What is the must have software?

What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would ...
6
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2answers
481 views

What is the difference between regular FPGA boards and FPGA boards for ASIC emulation?

I'm considering to buy a FPGA evaluation board for ASIC prototyping(makes HDL codes for designing chip that will be manufactured as real chip). On the market, there are not only regular FPGA boards, ...
6
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1answer
465 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
5
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5answers
1k views

Is it good practice to always assign initial value and reset signals in digital design?

I have read that initial values to a signal can be set in an FPGA since the design is "loaded into it" after power up. However, in ASICs we can only rely on a reset signal to put all signals into a ...
5
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3answers
2k views

Is it possible to “crack” an ASIC?

Could someone break an ASIC? If an ASIC is a fully customized, app-specific CPU, is possible to reverse engineer it? I'd imagine the answer in general is no, since to me the only way to do this ...
5
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3answers
295 views

What options do I have when synthesising control registers?

When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those? For instance: Do you keep them on their own clock ...
5
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1answer
920 views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
5
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1answer
284 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
4
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5answers
9k views

Designing a 4-bit ALU to compute various functions

I've been working on designing an ALU that calculates various functions but I don't really know how to separate each function from one another. The inputs are 4-bit numbers A and B. I have a decoder ...
4
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2answers
747 views

ASIC Shuttle Service Disadvantages?

Im trying to learn a bit about the techniques to create an ASIC. I found that the NRE-Costs are the biggest cost part which means the creationg of the masks and you get a minimum number of ASICs back. ...
4
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3answers
2k views

Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process

I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and ...
4
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3answers
320 views

Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?

I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
3
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3answers
1k views

Gate array propagation delay times

This is kind of a simple question I haven't been able to find an answer for. According to my notes, propagation delay increases as supply voltage decreases. While intuitively I would think it would ...
3
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2answers
12k views

Please explain tech.lef , tech.lib

Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
3
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1answer
1k views

Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
3
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2answers
2k views

Clock Domain Crossing for Pulse and Level Signal

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that? EDIT: After @...
3
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1answer
671 views

Price History of FPGA

My goal is to extrapolate (or estimate) the future prices of FPGAs and/or ASICs. Does anyone know of the price history of FPGAs or ASICs? I am looking for a source of information. I know that today ...
3
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1answer
171 views

Large SiGe ASICs for digital logic

I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a ...
3
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3answers
293 views

What do you call this- ASIC or SOC?

I am new to the field of electronics engineering as I'm originally an electrical engineering graduate (Read Power Systems, machines and HV engineering) so I studied only 'basic electronics' in my ...
3
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1answer
469 views

Power categories in ASIC design (Design Compiler)

I am currently working on the synthesis, with Synopsys' Design Compiler, of an AES encryption module. In the power reports there are three power categories specified : Switching Power Internal Power ...
3
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1answer
491 views

Triple modular redundancy (TMR) in hardware

I would like to know if there are already ASICs/FPGAs implemented on top triple modular redundancy for fault tolerance/if they themselves implement TMR for fault correction. Any reference to research ...
3
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1answer
423 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
3
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2answers
250 views

What material(s) are used in IC's as insulating layers between metal layers?

This question and the answers hits close to the topic. One picture shows it as SOD. Silicon-oxide dielectric? I'm aware that around/within the transistor, silicon oxide is grown for insulation where ...
3
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3answers
598 views

When might a standard cell optimized for zero wireload capacitance be used?

Some standard cell libraries include cells optimized for zero wireload capacitance. When might these be used? Are these used when the output drives a gate that's physically very close to the output? ...
2
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5answers
402 views

Are there fully open-source ASICs?

The Ethereum Foundation (an open-source project) will build an open-source ASIC to support its decentralised randomness beacon. To date, has the RTL of any ASIC been open-sourced or will the Ethereum ...
2
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3answers
852 views

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
2
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3answers
1k views

What are the general steps used in creating a ASIC?

I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered Once a logic design is tested on an FPGA it ...
2
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2answers
294 views

Can multi-project wafer service merge projects with different number of layers?

I would like to ask some help to better understand limitations of multi-project wafer services (MPW). In nutshell, i found about the service, that it merges many projects on wafer, so one project ...
2
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2answers
6k views

Gated clocks and clock enables in FPGA and ASICS

Please correct me if I am wrong. I have generally read that for FPGA's gating the master clock is a bad design practice and that one should use master clock & clock enable whenever circuit needs a ...
2
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3answers
250 views

Routing of an ASIC chip - time taken?

In a typical ASIC design cycle, how much time is taken by an EDA tool to complete the routing? Assume a fairly complex chip (like the Ivy Bridge). I've heard the entire chip design cycle is typically ...
2
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2answers
617 views

Huge on-die capacitor

The schematic of the LM113 precision reference shows a 75pF capacitor integrated in the IC. Looks huge to me. What's the limit when integrating capacitor on-die?
2
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2answers
160 views

How is the bias current reference value determined for CMOS circuit design?

In the few textbooks I'm reading on CMOS analog design, they all seem to have reference currents of \$10 \mu A\$ or similar that get mirrored, and there doesn't seem to be any discussion on how this ...
2
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2answers
1k views

Balancing Unbalanced Audio Inputs

I'm wanting to nicely balance some unbalanced inputs to a power amp for good CMRR, and because I'm feeling too lazy to start trying to closely match pairs of resistors, I'm looking at using a hi-fi ...
2
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3answers
161 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
2
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2answers
255 views

how slow are modelsim free licences?

I know in free licenses of modelsim / questa simulations run slower than the full version. But how slow? will it be 2x 3x 10x faster in the paid version? what about actel/microsemi free version ?
2
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1answer
844 views

Aggregate of 2 vectors in VHDL

I am checking what I can and cannot do in aggregating and concatenating in VHDL. while I can combine two vectors by concatenating them, I keep getting error if I use aggregate. I saw one answer here ...