Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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How do the three wires for each HDMI Channel relate to a single signal?
I'm working on an HDMI ASIC and the HDMI spec is very clear on everything except for the way that the +, -, and shield wires are used to transmit a given signal. The TDMS channels and the clock are ...
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Flash Memory on an ASIC
Are flash memory and ROM also considered integrated circuits? And so, is it possible to embed a flash memory or a ROM into an ASIC?
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In CMOS, can I assume the delay of a multiplexer is negligible compared to the delay of an inverter?
Let say I have a ring oscillator, and I modify the ring so that the output of an inverter is connected to an input of a 2-to-1 MUX, and the output of the MUX is connected to the input of the next ...
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How to measure the delay of one single inverter in ASIC?
In practice, is it feasible for a chip manufacture to reliably and accurately measure the delay of one single inverter in ASIC? If it is, how can one go about doing it?
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Convert area of ASIC into kilo-gate equivalent kGE
Is there any resource/datasheet where I can find the kilogate (kGE) of the various CMOS technologies? Essentially, I have a bunch of ASIC circuits with their areas given in mm2 that I want to convert ...
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What do you call this- ASIC or SOC?
I am new to the field of electronics engineering as I'm originally an electrical engineering graduate (Read Power Systems, machines and HV engineering) so I studied only 'basic electronics' in my ...
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Would shooting laser or UV light at an inverter make it permanently slower?
I'm studying the topic of cloning electronic circuits for my research. And I have a scenario as the following:
Chip A has two ring oscillators (RO1a and RO2a). And RO1a is faster than RO2a.
Chip B ...
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Why do embedded systems need to be programmable?
According to my understanding, certain types of embedded systems are dedicated to a particular task. Why, then, do engineers not transfer all the burden of processing onto the hardware in the form of ...
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ASIC Shuttle Service Disadvantages?
Im trying to learn a bit about the techniques to create an ASIC. I found that the NRE-Costs are the biggest cost part which means the creationg of the masks and you get a minimum number of ASICs back.
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Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?
I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
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Please explain tech.lef , tech.lib
Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
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What topologies are used for ultra-low-power CMOS DACs?
What schematics, topologies or algorithms are suitable for ultra-low-power DAC design? You can assume the following design requirements (they are flexible):
Full custom CMOS design (this is not a ...
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Gated clocks and clock enables in FPGA and ASICS
Please correct me if I am wrong. I have generally read that for FPGA's gating the master clock is a bad design practice and that one should use master clock & clock enable whenever circuit needs a ...
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Area vs Operating Frequency in asic synthesis
I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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ASIC vs ? -- Performance & Cost
I'm interested in creating a custom linux based solution that will crunch sha256 cryptographic algorithms at insane levels of speed. I'm also on a limited budget... I have no background in EE but I ...
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When might a standard cell optimized for zero wireload capacitance be used?
Some standard cell libraries include cells optimized for zero wireload capacitance. When might these be used?
Are these used when the output drives a gate that's physically very close to the output? ...
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Triple modular redundancy (TMR) in hardware
I would like to know if there are already ASICs/FPGAs implemented on top triple modular redundancy for fault tolerance/if they themselves implement TMR for fault correction. Any reference to research ...
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What can go wrong when producing an ASIC from an FPGA-verified verilog design?
Given a Verilog design fully validated on an FPGA prototyping system, and someone who has never done an ASIC before, what are the chances that a service like CMP will ship fully usable chips on the ...
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RTL compiler timing constraint error
I need to know the maximum clock frequency of my design. But RTL compiler does not give me the max frequency if I dont give a timing constraint. (Actually I am not sure if it will give me the ...
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Unit of area in RTL Compiler
After compiling my design using RTL compiler targeting 45nm library, the tool gives me an area report as below:
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Has an FPGA ever caused health issues?
Considering the number of people here who work closely with always on FPGAs, ASICs etc, and how materials react to heat, etc. Are there any known health issues when dealing with
hot electronics ...
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What are the general steps used in creating a ASIC?
I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered
Once a logic design is tested on an FPGA it ...
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Routing of an ASIC chip - time taken?
In a typical ASIC design cycle, how much time is taken by an EDA tool to complete the routing?
Assume a fairly complex chip (like the Ivy Bridge). I've heard the entire chip design cycle is typically ...
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Gate array propagation delay times
This is kind of a simple question I haven't been able to find an answer for.
According to my notes, propagation delay increases as supply voltage decreases. While intuitively I would think it would ...
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set and reset of D flip-flops : always physically present?
On various technology (discrete, ASIC, FPGA), I'd like to know if the asynchronous signals set and reset are always present on D (edge-triggered) flip-flops. If not how the reset process can be ...
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How does program execution happen in firmware?
I have heard from people working in firmware domain, that there is no Operating system controlling firmware (eg firmware in a USB drive). There is just a single thread running in a while loop waiting ...
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What are the practical uses of ASIC?
Microcontrollers, FPGAs, ASIC (Application-specific integrated circuit) all are used for similar type of applications (at different levels). I know about microcontrollers and FPGAs. But what is an ...
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Regular or Irregular Hardware?
I have a hardware structure (described in logic diagram consisting of adders and multipliers) that is extremely regular, i.e., one small hardware is repeated again and again in the structure with ...
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Price History of FPGA
My goal is to extrapolate (or estimate) the future prices of FPGAs and/or ASICs.
Does anyone know of the price history of FPGAs or ASICs? I am looking for a source of information.
I know that today ...
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ASIC Verfication Do I need to verify all possible combinations?
I'm currently doing ASIC Black box Verification.
Suppose I got a module with 200 input ports with 12 bit width each and a one output port with 64 bit width. Lets say, its pure combinational inside.
<...
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Is every in-field stimulus replay-able during simulation?
I always though that simulation of hardware architectures (FPGA/ASIC) cannot cover every possible stimulus and corner-case that can be encountered in real conditions, and that hardware-accelerated ...
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How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
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Where can I find the maximum value of length and width that a PMOS or NMOS supports?
I searched the web but didn't come up with something good. I am using the 0_25umMODEL_TYP.md module of spice. I was wondering, what is the maximum size transistor ...
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Reset: synchronous vs asynchronous
I've been working with fpgas for years, and always used synchronous resets for every parts (that need it) of my circuits. It helps the circuit to be globally reset at a given clock cycle.
However, I ...
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Huge on-die capacitor
The schematic of the LM113 precision reference shows a 75pF capacitor integrated in the IC. Looks huge to me. What's the limit when integrating capacitor on-die?
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Getting starting designing CMOS ASIC - What is the must have software?
What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would ...
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Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process
I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and ...
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What options do I have when synthesising control registers?
When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those?
For instance:
Do you keep them on their own clock ...
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Designing a 4-bit ALU to compute various functions
I've been working on designing an ALU that calculates various functions but I don't really know how to separate each function from one another. The inputs are 4-bit numbers A and B. I have a decoder ...
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Balancing Unbalanced Audio Inputs
I'm wanting to nicely balance some unbalanced inputs to a power amp for good CMRR, and because I'm feeling too lazy to start trying to closely match pairs of resistors, I'm looking at using a hi-fi ...
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How much does it cost to have a custom ASIC made?
I have browsed several ASIC manufacturer's webs, but I haven't found an actual number.
I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
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