Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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207 views

How is the bias current reference value determined for CMOS circuit design?

In the few textbooks I'm reading on CMOS analog design, they all seem to have reference currents of \$10 \mu A\$ or similar that get mirrored, and there doesn't seem to be any discussion on how this ...
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1k views

Balancing Unbalanced Audio Inputs

I'm wanting to nicely balance some unbalanced inputs to a power amp for good CMRR, and because I'm feeling too lazy to start trying to closely match pairs of resistors, I'm looking at using a hi-fi ...
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363 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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1answer
2k views

Aggregate of 2 vectors in VHDL

I am checking what I can and cannot do in aggregating and concatenating in VHDL. while I can combine two vectors by concatenating them, I keep getting error if I use aggregate. I saw one answer here ...
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1answer
217 views

Computational complexity of current netlist matching algorithms

I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
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96 views

Is every in-field stimulus replay-able during simulation?

I always though that simulation of hardware architectures (FPGA/ASIC) cannot cover every possible stimulus and corner-case that can be encountered in real conditions, and that hardware-accelerated ...
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126 views

Meaning of two NOT gates in parallel

Background -- I have in my possession a schematic for an ASIC NMOS chip developed between around 1985 until 1992. It's copyrighted and I'd rather not get into the details of of what its for, but my ...
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1answer
416 views

VHDL: Optmize signal comparisons for synthesis

As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
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1answer
2k views

RTL compiler timing constraint error

I need to know the maximum clock frequency of my design. But RTL compiler does not give me the max frequency if I dont give a timing constraint. (Actually I am not sure if it will give me the ...
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339 views

Is there a fieldbus with more than 250 nodes per segment?

We plan to realize a sensor cable several 1000m long which has ideally every 1-2m a magnetic field sensor on a small 10x30mm platine with microprocessor/FPGA for DSP and I2C on chip communication. ...
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1answer
388 views

how do you know the each parameter values of SDC at the first time?

when we do synthesis with SDC. we should be used with SDC. But I want to know what if you are in situation where the synthesis of yours is the first time, also the company does not even did synthesis ...
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2k views

Setup and Hold time VS temperature (and temperature inversion)

So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is ...
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3k views

How to obtain the (estimate) equivalent gate count for a FPGA design?

I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by ...
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280 views

Would shooting laser or UV light at an inverter make it permanently slower?

I'm studying the topic of cloning electronic circuits for my research. And I have a scenario as the following: Chip A has two ring oscillators (RO1a and RO2a). And RO1a is faster than RO2a. Chip B ...
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138 views

Are FPGAs for experimentation alone?

I have been reading about FPGAs recently and found that they have a lot of applications in many fields. I also read an article that they are used for testing purposes alone. Are FPGAs only for that? ...
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4answers
606 views

Is an ethernet switch considered as an ASIC?

I work as an electronic reliability engineer. In order to estimate the reliability of integrated circuits, I need to know their type. Thus my question. Is this ethernet switch Marvell Link Street-...
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349 views

ASIC fabrication companies [closed]

What is the cheapest way to synthesize ASICs in small quantities? (5-10 chips). I'm asking for a specific company, not method.
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520 views

What topologies are used for ultra-low-power CMOS DACs?

What schematics, topologies or algorithms are suitable for ultra-low-power DAC design? You can assume the following design requirements (they are flexible): Full custom CMOS design (this is not a ...
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77 views

Shared IC tape out

I have a IC design about 300*300 micrometers. Due to the high cost of IC tape out, is it possible to fabricate the IC jointly with other people? Does the company have such a service?
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122 views

Is there an easy way to physically implement a simple digital circuit?

I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
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218 views

Gate and routing delays as a function of voltage and temperature

As I understand from watching overclocking videos, the maximum operating frequency of a digital ASIC is a function of voltage and temperature. Specifically, it seems that the maximum operating ...
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1answer
116 views

Can we connect both ASIC and an FPGA both to the same physical output Ethernet ports at the same time? [closed]

I am doing simulation of my research design on single FPGA, in which I simulated two switching chips ASIC and an FPGA. I mean, I simulated single FPGA working as two chips, and connected them so that ...
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301 views

Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
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627 views

Flash Memory on an ASIC

Are flash memory and ROM also considered integrated circuits? And so, is it possible to embed a flash memory or a ROM into an ASIC?
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1k views

Convert area of ASIC into kilo-gate equivalent kGE

Is there any resource/datasheet where I can find the kilogate (kGE) of the various CMOS technologies? Essentially, I have a bunch of ASIC circuits with their areas given in mm2 that I want to convert ...
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1answer
111 views

65nm silicon-germanium

The Wikipedia page on silicon-germanium states that AMD and IBM worked on a 65nm SiGe process. Unfortunately the source is no longer up and I cannot find more information about the 65nm SiGe process. ...
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11k views

Understanding combinational feedback loops

Please give me a simple example of a verilog code that results in combo feedback loop. Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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6k views

Understanding (PVT) Corners

1) Do corners always refer to PVT corners in ASIC design? Or are there any other elements involved in a corner? 2) On what basis are corners named "Slow", "Typical" & "Fast"? 3) What factors ...
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29 views

SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops

Given a SystemVerilog design modeling an ASIC, how can I enforce the rule that all logic/reg elements that are used in flip-flops should not be initialized to a certain value? Is there a directive ...
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2answers
449 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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1answer
505 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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1answer
99 views

Can I order PCB/chip manufacture from provided LOTOS specification?

Is there a way to automatically deduct PCB and/or chip design from formal problem specification of a problem (task) which supposed to be solved on a PCB/chip? I'm currently implementing solution with ...
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2answers
1k views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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214 views

Is there an “additive manufacturing” method to make an ASIC?

Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting ...
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1answer
2k views

Where can I find the maximum value of length and width that a PMOS or NMOS supports?

I searched the web but didn't come up with something good. I am using the 0_25umMODEL_TYP.md module of spice. I was wondering, what is the maximum size transistor ...
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1answer
35 views

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
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1answer
393 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
216 views

Is RAM with read ahead (Look ahead) possible?

Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports? A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
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369 views

Area vs Operating Frequency in asic synthesis

I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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258 views

Beyond liquid helium cooling

Liquid helium has a boiling point of around -269°C and is used by overclockers. It has led to various world records (e.g. see here and here). What cooling technology can beat liquid helium for the ...
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304 views

Has an FPGA ever caused health issues?

Considering the number of people here who work closely with always on FPGAs, ASICs etc, and how materials react to heat, etc. Are there any known health issues when dealing with hot electronics ...
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89 views

Designing ASIC Chip for Enterprise [closed]

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring ...
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200 views

How do the three wires for each HDMI Channel relate to a single signal?

I'm working on an HDMI ASIC and the HDMI spec is very clear on everything except for the way that the +, -, and shield wires are used to transmit a given signal. The TDMS channels and the clock are ...
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202 views

Good practices for full-custom IC measurement? [closed]

I am a Junior Analog IC Designer and I want to characterize a full-custom IC. The thing is that I want to do it well and I don't know any reference with good practices and PCB design guidelines for ...
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1answer
112 views

Can FPGAs be emulated?

Can FPGAs be emulated on general purpose computers? As per Church-Turing thesis all Turing machines can be emulated on the universal Turing machine. So if the FPGA can emulate processors, can the ...
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612 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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128 views

Mixing reset and non reset registers

If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way... ...
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1answer
222 views

Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me: 1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
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178 views

Regular or Irregular Hardware?

I have a hardware structure (described in logic diagram consisting of adders and multipliers) that is extremely regular, i.e., one small hardware is repeated again and again in the structure with ...
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What is meant by process “performance”?

I am reading the product page for TSMC's 20nm process. It states Compared to its 28nm node, the 20nm process provides 15% better performance and can reduce total power consumption by a third. What ...