Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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Computational complexity of current netlist matching algorithms

I understand that the problem of matching two netlists could be reduced to the graph isomorphism problem which is NP-intermediate. Apart from that what are the complexity results of some of the ...
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Is every in-field stimulus replay-able during simulation?

I always though that simulation of hardware architectures (FPGA/ASIC) cannot cover every possible stimulus and corner-case that can be encountered in real conditions, and that hardware-accelerated ...
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1answer
288 views

VHDL: Optmize signal comparisons for synthesis

As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
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1answer
2k views

RTL compiler timing constraint error

I need to know the maximum clock frequency of my design. But RTL compiler does not give me the max frequency if I dont give a timing constraint. (Actually I am not sure if it will give me the ...
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1answer
325 views

how do you know the each parameter values of SDC at the first time?

when we do synthesis with SDC. we should be used with SDC. But I want to know what if you are in situation where the synthesis of yours is the first time, also the company does not even did synthesis ...
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1answer
2k views

Setup and Hold time VS temperature (and temperature inversion)

So I know that propagation delay and timing inside an ASIC are affected by temperature. In the old days things went faster when colder and slower when hotter. Now at 90nm and below there is ...
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2answers
3k views

How to obtain the (estimate) equivalent gate count for a FPGA design?

I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by ...
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2answers
1k views

How fast can a modern ASIC be clocked?

Modern CPUs today are commonly clocked in the 3-4 GHz range. How fast can typical modern ASICs be clocked? For example if I were building a commodity ASIC for something like a disk drive or ...
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1answer
278 views

Would shooting laser or UV light at an inverter make it permanently slower?

I'm studying the topic of cloning electronic circuits for my research. And I have a scenario as the following: Chip A has two ring oscillators (RO1a and RO2a). And RO1a is faster than RO2a. Chip B ...
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4answers
404 views

Is an ethernet switch considered as an ASIC?

I work as an electronic reliability engineer. In order to estimate the reliability of integrated circuits, I need to know their type. Thus my question. Is this ethernet switch Marvell Link Street-...
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4answers
5k views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
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331 views

ASIC fabrication companies [closed]

What is the cheapest way to synthesize ASICs in small quantities? (5-10 chips). I'm asking for a specific company, not method.
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1answer
514 views

What topologies are used for ultra-low-power CMOS DACs?

What schematics, topologies or algorithms are suitable for ultra-low-power DAC design? You can assume the following design requirements (they are flexible): Full custom CMOS design (this is not a ...
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1answer
383 views

What runs a g-shock watch?

I am currently trying to learn more about watches and what it takes to build them. I currently own a watch called the G-Shock 7900b and was wondering what runs it inside. Here is a link to the watch: ...
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1answer
122 views

Is there an easy way to physically implement a simple digital circuit?

I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
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2answers
198 views

Gate and routing delays as a function of voltage and temperature

As I understand from watching overclocking videos, the maximum operating frequency of a digital ASIC is a function of voltage and temperature. Specifically, it seems that the maximum operating ...
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1answer
109 views

Can we connect both ASIC and an FPGA both to the same physical output Ethernet ports at the same time? [closed]

I am doing simulation of my research design on single FPGA, in which I simulated two switching chips ASIC and an FPGA. I mean, I simulated single FPGA working as two chips, and connected them so that ...
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256 views

Can the same net-list file be used for ASIC design flow as well as FPGA design flow?

I have mostly worked on front-end part and don't know much about back-end stuff. I have gone through the reading about the various abstraction levels of design flows of FPGAs and ASICs. I was ...
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547 views

Flash Memory on an ASIC

Are flash memory and ROM also considered integrated circuits? And so, is it possible to embed a flash memory or a ROM into an ASIC?
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1answer
924 views

Convert area of ASIC into kilo-gate equivalent kGE

Is there any resource/datasheet where I can find the kilogate (kGE) of the various CMOS technologies? Essentially, I have a bunch of ASIC circuits with their areas given in mm2 that I want to convert ...
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1answer
95 views

65nm silicon-germanium

The Wikipedia page on silicon-germanium states that AMD and IBM worked on a 65nm SiGe process. Unfortunately the source is no longer up and I cannot find more information about the 65nm SiGe process. ...
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1answer
5k views

Understanding (PVT) Corners

1) Do corners always refer to PVT corners in ASIC design? Or are there any other elements involved in a corner? 2) On what basis are corners named "Slow", "Typical" & "Fast"? 3) What factors ...
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305 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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1answer
98 views

Can I order PCB/chip manufacture from provided LOTOS specification?

Is there a way to automatically deduct PCB and/or chip design from formal problem specification of a problem (task) which supposed to be solved on a PCB/chip? I'm currently implementing solution with ...
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2answers
941 views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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4answers
193 views

Is there an “additive manufacturing” method to make an ASIC?

Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting ...
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1answer
2k views

Where can I find the maximum value of length and width that a PMOS or NMOS supports?

I searched the web but didn't come up with something good. I am using the 0_25umMODEL_TYP.md module of spice. I was wondering, what is the maximum size transistor ...
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1answer
83 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
303 views

Is there a fieldbus with more than 250 nodes per segment?

We plan to realize a sensor cable several 1000m long which has ideally every 1-2m a magnetic field sensor on a small 10x30mm platine with microprocessor/FPGA for DSP and I2C on chip communication. ...
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1answer
399 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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1answer
204 views

Is RAM with read ahead (Look ahead) possible?

Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports? A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
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344 views

Area vs Operating Frequency in asic synthesis

I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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193 views

Beyond liquid helium cooling

Liquid helium has a boiling point of around -269°C and is used by overclockers. It has led to various world records (e.g. see here and here). What cooling technology can beat liquid helium for the ...
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299 views

Has an FPGA ever caused health issues?

Considering the number of people here who work closely with always on FPGAs, ASICs etc, and how materials react to heat, etc. Are there any known health issues when dealing with hot electronics ...
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1answer
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Designing ASIC Chip for Enterprise [closed]

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring ...
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197 views

How do the three wires for each HDMI Channel relate to a single signal?

I'm working on an HDMI ASIC and the HDMI spec is very clear on everything except for the way that the +, -, and shield wires are used to transmit a given signal. The TDMS channels and the clock are ...
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1answer
194 views

Good practices for full-custom IC measurement? [closed]

I am a Junior Analog IC Designer and I want to characterize a full-custom IC. The thing is that I want to do it well and I don't know any reference with good practices and PCB design guidelines for ...
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1answer
315 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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103 views

Mixing reset and non reset registers

If you must mix synchronous reset and non reset flops in a single always block, would this be the correct way... ...
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1answer
207 views

Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me: 1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
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1answer
174 views

Regular or Irregular Hardware?

I have a hardware structure (described in logic diagram consisting of adders and multipliers) that is extremely regular, i.e., one small hardware is repeated again and again in the structure with ...
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What is meant by process “performance”?

I am reading the product page for TSMC's 20nm process. It states Compared to its 28nm node, the 20nm process provides 15% better performance and can reduce total power consumption by a third. What ...
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588 views

How does asynchronous and synchronous reset signal affect the setup and hold time in a Flip Flop?

Does the async. and sync. reset signal follow the setup and hold time conditions of flip flop? If so how would they affect the output?
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174 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
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2answers
108 views

How does a device that is RF enabled power up the main CPU by way of RF?

Suppose you have a device such as a wireless video camera and the only way to power on the device is by way of RF. If the video camera has a CPU how can the baseband IC power up this CPU ? Is it ...
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788 views

How is the difference between sdf back annotation and spf back annotation?

I'm a rtl engineer. I'm confused between the difference of sdf and spf back annotation. As I know sdf came from STA( PT) and SPF came from STAR-RC. So In my experiance, the sdf used to timing close ...
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2answers
3k views

How to find high fanout nets?

In the timing report of a synthesis with Synopsys VCS, a warning states: Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
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9k views

Understanding combinational feedback loops

Please give me a simple example of a verilog code that results in combo feedback loop. Why are these feedback loops undesired in your design? How to interpret blocking vs non blocking assignments in ...
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In CMOS, can I assume the delay of a multiplexer is negligible compared to the delay of an inverter?

Let say I have a ring oscillator, and I modify the ring so that the output of an inverter is connected to an input of a 2-to-1 MUX, and the output of the MUX is connected to the input of the next ...
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Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...