Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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68 views

How to find a design house with dynamic memory device support? [closed]

I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...
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Clarification on terminology : RF Signal

I frequently come across the term 'RF Signal' in circuits for ex in the below picture, please ignore the functionality of circuit not important.: I understand RF means Radio frequency but what I dont ...
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126 views

Which fab for DRAM device? (ASIC design at Europractice)

I would like to ask for advice. Europractice supports many fabs and technologies for custom asic design (fab list). Lib support list of those technologies are public (for example UMC 130 nm LL). I ...
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589 views

Connect PCIe x1 port to an ASIC PCIe x4 [closed]

I want to connect a microcontroller with a PCIe x1 port to an ASIC with PCIe x4 interface. It is not possible to connect microcontroller to lane 0 of ASIC, and it should be connected to other lanes (...
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149 views

Baseband Processor

If a device can only be activated by way of RF then I would tend to believe that the BB processor (embedded via ASIC design) would need to be active and powered on yes ? If correct then does it have ...
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416 views

Are there any alternatives to ASIC chips? [closed]

Are there any other mixed-signal integrated circuit embedded systems (or alternative solutions) which are faster than ASIC in terms of performance (let say for a high-efficiency Bitcoin miner)?
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89 views

data bus power consumption

In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing: use a mux for the read data of each master, so that if the ...
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303 views

ASIC Power supply requirements

I am a newbie in ASIC design process and have a question. What is difference (or pros and cons) of shorting the voltage supply pins(which have the same voltage requirements) in package level or in die(...
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117 views

Power analysis after placement and routing of ASIC

How can I procure the files stating the details of power consumption of the chip after PNR in SOC Cadence Encounter?
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2answers
238 views

Cadence SoC encounter

I am trying to create the layout of my design for an 8 bit multiplier accumulator in SoC Cadence encounter tool. After routing the design using wroute command, the ...
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217 views

set and reset of D flip-flops : always physically present?

On various technology (discrete, ASIC, FPGA), I'd like to know if the asynchronous signals set and reset are always present on D (edge-triggered) flip-flops. If not how the reset process can be ...
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38 views

RS232 to ARINC429 Converter

There is a device 1 that outputs some data on RS-232 serial lines. There is another device 2 that receives data on its ARINC-429 bus. I have to connect these such that device 1 data goes into device 2....
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35 views

What is the delay incurred by ternary content-addressable memory (TCAM)?

What is the cost (in terms of delay) of using TCAM? How do they compare with SRAM and DRAM? I understand their use cases are different. But assume, for an application, I can do an operation using ...
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43 views

FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
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Power analysis using Synopsys Design Compiler

I am trying to generate power report using Synopsys DC compiler. At first I have generated VCD file using Modelsim simulator, which I have converted to SAIF file using "vcd2saif" command. Then I ...
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135 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
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Innovus MMMC import

I am exploring Genus and Innovus tools, I noticed to import a design in Innovus we have to import MMMC.tcl file, is this file provided or have to be generated by Genus ? or needs to be written ...
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48 views

Flipflop value a long time after startup

After power up in an ASIC, is it save to assume that all flipflops are in a stable state ('0' or '1')? I do not care in which stable state they are, but it is crucial that all metastability has ...
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80 views

Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]

If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1. But if LSB comes in first, how can we come up with ...
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213 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
70 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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30 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
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Do Broadcom's Ethernet chipsets need special software to operate?

I want to implement an Ethernet switch using Broadcom's chips. Are singing an NDA and getting the datasheets enough to work with the chips? I have heard that the chips must be programmed by a special ...
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43 views

How to simulate a piezoresistive pressure sensing MEMs layout without COMSOL?

I have a masks layout of a Piezoresistive MEMs pressure device that I've designed in LEdit(Tanner Tools Eda). The device consists of 4 piezoresistors bonded onto a thin diaphragm which deforms ...
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38 views

How can I access process node data sheets?

I am searching for process node data sheets. Specifically, I'm interested in TSMC's 16nm, 12nm, 10nm, 7nm nodes, as well as Samsung's 14nm, 10nm nodes. I did not find anything with Google. How can I ...
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119 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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84 views

Gated integrator IC, non continuous

Can anyone give me any suggestions for some good gated voltage integrators that aren't continuous, and more like a boxcar integrator? I want to integrate the the total voltage across a pulse coming ...
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1answer
101 views

How to scale output of butterfly unit radix 2 for further stages?

I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for ...
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115 views

How to measure dynamic power consumption of each component of a Microcontroller?

I am interested to get the dynamic power consumption of each of the component of a micro-controller. Can I do it by adding the power lines in place and route (PAR)? The purpose of it to get the more ...
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572 views

ASIC verification of a FIFO with “n” unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
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81 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
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669 views

How to measure the delay of one single inverter in ASIC?

In practice, is it feasible for a chip manufacture to reliably and accurately measure the delay of one single inverter in ASIC? If it is, how can one go about doing it?
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Unit of area in RTL Compiler

After compiling my design using RTL compiler targeting 45nm library, the tool gives me an area report as below: ...
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286 views

Is it Possible to Design an Entire Operating System or App using ASIC Chips? [closed]

ASIC chips are hundreds of times faster than traditional chips. Is it possible to design an entire operating system or application using a full custom ASIC chip? Based on what I've read I understand ...
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2answers
47 views

Maximum power draw density of digital ASIC

Given a process node (e.g. TSMC's 16nm FinFET+) what is the maximum power per mm2 that a digital ASIC can draw? Secondary question: Assuming liquid nitrogen cooling, what would be the bottleneck ...
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203 views

ASIC v.s. State Machine - same difference? [closed]

Are ASIC chips the equivalent of "State Machines" in computer science ? There are no "programs" or "instructions" that are executed. All the changes occure because of the inputs on the gates when the ...
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451 views

How to determine No. of Transistors in a chip? [closed]

How can I know the exact No. of transistors in my chip before fabrication and after fabrication? It is possible to count transistors using LVS (Layout Vs. Schematic), but its valid for Final Layout ...
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236 views

How can we use D flip flop and a combinational circuit to retain a bit?

I am trying to solve a problem, which involves designing a gate level circuit, and I'm stuck on the last part of the problem. The last part wants me to retain the carry flag generated from the adder ...
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Chip vs printed circuit board [closed]

What is the difference between a chip, wafer, and PCB? Are PCB individual components cut out from bigger wafers?
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138 views

Whats the difference between an FPGA and an ASIC [closed]

I know what an FPGA and ASIC are. However what I want to know is what is the difference with cost and time. How long does it take to build an FPGA? How long does it take to build an ASIC? How much ...