Questions tagged [axi4]

Question related to the Advanced Microcontroller Bus Architecture (AMBA) based Advanced eXtensible Interface (AXI) protocol. This interface is commonly used in a lot of present-day SoC's

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AXI Protocol Checker IP reports errors on AXI_ERRS_RID and AXI_AUXM_RCAM_OVERFLOW

AXI Protocol Checker IP reports errors on AXI_ERRS_RID and AXI_AUXM_RCAM_OVERFLOW which are pc_status bits 59 and 78 respectively. My AXI code is located at here (need to uncomment code block lines ...
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25 views

AXI arvalid signal issue

I have question about AXI arvalid signal used for interfacing with DDR axi controller in Zynq. If I do not remove i_axi_arready , I will have deadlock issue. If I remove i_axi_arready , I will have ...
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43 views

AXI4 address calculation for INCR bursts

I'm going through the AXI4 specification at https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf. On page A3-47, a number of equations for calculating addresses are given: ...
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90 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
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40 views

What does the T stand for in AXI4-Stream's TDATA, TVALID, TREADY, etc.?

In the AXI4-Stream protocol, the names of the signal that make up a stream are prefixed with T: TDATA, ...
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49 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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AXI4-Stream TVALID stuck low between VDMA and video output block

I'm trying to buffer a single frame of video using a VDMA block on a Trenz TE0712 board (artix-7 based development board), based on a few examples (specifically Numato's framebuffer example and Xilinx'...
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Microzed (z7010) AXI4 output to Pmod I/O on Carrier card

I am new developer with zynq7000 SoC. I am working with MicroZed board (z7010) and I want to implement a PWM technique for two switches in one leg. I have already wrote the VHDL code and also I made ...
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1answer
24 views

Validity of AWADDR once AWREADY is asserted in AXI4-Lite interface

This question is a follow-up to Relationship between AWVALID and WVALID in AXI4-Lite interface, from which I learned that AWVALID and WVALID have no specific timing relationship. Now I have a slightly ...
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55 views

Relationship between AWVALID and WVALID in AXI4-Lite interface

I am implementing an AXI4-Lite slave interface in FPGA and I want to have the read/write operations to complete in as few clock cycles as possible. With that in mind, can I assume any specific ...
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164 views

What happens when there is a simultaneous Read and Write launched to the same address in AXI3/4?

I have a doubt regarding the AXI3/4 protocol. Assume a hypothetical scenario where a single master issues a valid Read and Write transaction to the same address simultaneously. From the AXI ...
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50 views

AXI4 Interconnect blocks transactions?

I have an AXI4 master on one board and AXI slave on the other (BRAM controller). The data is transferred using Chip2Chip and Aurora as shown in the figure. I would like to initiate several burst ...
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189 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...