Questions tagged [axi4]

Question related to the Advanced Microcontroller Bus Architecture (AMBA) based Advanced eXtensible Interface (AXI) protocol. This interface is commonly used in a lot of present-day SoC's

Filter by
Sorted by
Tagged with
1
vote
0answers
28 views

AXI4-Stream TVALID stuck low between VDMA and video output block

I'm trying to buffer a single frame of video using a VDMA block on a Trenz TE0712 board (artix-7 based development board), based on a few examples (specifically Numato's framebuffer example and Xilinx'...
0
votes
0answers
16 views

Microzed (z7010) AXI4 output to Pmod I/O on Carrier card

I am new developer with zynq7000 SoC. I am working with MicroZed board (z7010) and I want to implement a PWM technique for two switches in one leg. I have already wrote the VHDL code and also I made ...
0
votes
1answer
19 views

Validity of AWADDR once AWREADY is asserted in AXI4-Lite interface

This question is a follow-up to Relationship between AWVALID and WVALID in AXI4-Lite interface, from which I learned that AWVALID and WVALID have no specific timing relationship. Now I have a slightly ...
1
vote
1answer
46 views

Relationship between AWVALID and WVALID in AXI4-Lite interface

I am implementing an AXI4-Lite slave interface in FPGA and I want to have the read/write operations to complete in as few clock cycles as possible. With that in mind, can I assume any specific ...
2
votes
1answer
62 views

What happens when there is a simultaneous Read and Write launched to the same address in AXI3/4?

I have a doubt regarding the AXI3/4 protocol. Assume a hypothetical scenario where a single master issues a valid Read and Write transaction to the same address simultaneously. From the AXI ...
0
votes
0answers
34 views

AXI4 Interconnect blocks transactions?

I have an AXI4 master on one board and AXI slave on the other (BRAM controller). The data is transferred using Chip2Chip and Aurora as shown in the figure. I would like to initiate several burst ...
2
votes
1answer
123 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...