Questions tagged [axi4]

Question related to the Advanced Microcontroller Bus Architecture (AMBA) based Advanced eXtensible Interface (AXI) protocol. This interface is commonly used in a lot of present-day SoC's

Filter by
Sorted by
Tagged with
0
votes
1answer
46 views

AXI Stream Master - M_AXIS_TVALID not always be '1' during a transaction and M_AXIS_TLAST

I am implementing my AXI Stream Master module which can be use with Vivado DMA module. The connection of module is shown: I have 3 questions: 1.) Could the "m_axis_tvalid" signal be non ...
0
votes
0answers
52 views

FPGA AXI module development - synchronisation

I am trying to understand AXI interface and have one problem. My module should work as a slave, Vivado has generated required wrappers. Master will be filling 4 registers. I didn't find any specific ...
1
vote
1answer
100 views

AXI: Restrictions on slave address spaces?

Does the AXI specification impose any restrictions on the address space of slaves? I've read the latest version of the AXI specification (chapters A1-C2, ARM IHI 0022H) and could not find anything ...
1
vote
1answer
63 views

How to implement an interconnection matrix in VHDL?

I was reading through the documentation of the AXI standard when I came across the interconnection matrix shown below. In short, the interconnection matrix provides a path for several masters to ...
1
vote
1answer
259 views

Determining AXI4-stream Data FIFO size, understanding Packet Mode?

I want to take a standard AXI4-stream Data FIFO IP core and use it for data frame encapsulation for both the Ethernet and TCP/UDP layers. When packing a header onto the packets, I need to know the ...
0
votes
0answers
41 views

UART Transmitter and Receiver on AXI bus

I designed two components: UART Transmitter and UART Receiver (sends/receives 8 bits of data). Both Tx and Rx are working fine but I'm unable to wrap them in a AXI bus interface component. My UART ...
0
votes
0answers
18 views

Physical lines of an AXI4 bus

How many physical lines does an AXI4 bus require? How do signals described in the standard map to physical lines?
0
votes
0answers
56 views

AXI4 Pipelining

Given that there is no explicit ordering on AR after R has began transfer, is it possible to initiate a new AR handshake during the transmission of R? Also, does Xilinx IP support this optimization? ...
0
votes
0answers
305 views

AXI STREAM FIFO VHDL Implementation

Is this a right implementation of an axi stream fifo? ...
1
vote
1answer
326 views

AXI WSTRB and AWADDR issue with overlapping writes

I am having issue with AXI Protocol Checker pc_status[22] AXI_ERRM_WSTRB . Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size and ...
1
vote
1answer
44 views

Interpretation of pc_status bit location from Xilinx AXI Protocol Checker IP

In the pc_status error bit location , is it bit #32 because in the following simulation waveform, BVALID is never asserted high during the time when pc_status error bit #32 is asserted ?
0
votes
2answers
224 views

AXI4 address calculation for INCR bursts

I'm going through the AXI4 specification at https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf. On page A3-47, a number of equations for calculating addresses are given: ...
0
votes
2answers
168 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
0
votes
1answer
126 views

What does the T stand for in AXI4-Stream's TDATA, TVALID, TREADY, etc.?

In the AXI4-Stream protocol, the names of the signal that make up a stream are prefixed with T: TDATA, ...
1
vote
1answer
385 views

Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
0
votes
1answer
57 views

Validity of AWADDR once AWREADY is asserted in AXI4-Lite interface

This question is a follow-up to Relationship between AWVALID and WVALID in AXI4-Lite interface, from which I learned that AWVALID and WVALID have no specific timing relationship. Now I have a slightly ...
1
vote
1answer
250 views

Relationship between AWVALID and WVALID in AXI4-Lite interface

I am implementing an AXI4-Lite slave interface in FPGA and I want to have the read/write operations to complete in as few clock cycles as possible. With that in mind, can I assume any specific ...
3
votes
1answer
1k views

What happens when there is a simultaneous Read and Write launched to the same address in AXI3/4?

I have a doubt regarding the AXI3/4 protocol. Assume a hypothetical scenario where a single master issues a valid Read and Write transaction to the same address simultaneously. From the AXI ...
0
votes
0answers
58 views

AXI4 Interconnect blocks transactions?

I have an AXI4 master on one board and AXI slave on the other (BRAM controller). The data is transferred using Chip2Chip and Aurora as shown in the figure. I would like to initiate several burst ...
2
votes
1answer
471 views

AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly ...