# Questions tagged [boolean-algebra]

In mathematics and mathematical logic, boolean algebra is the branch of algebra in which the values of the variables are the truth values true and false, usually denoted 1 and 0 respectively. Boolean algebra is used in the analysis and simplification of digital (logic) circuits

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### How do I decompose 6 or more variable truth table to groups of 4 or 3 variable truth table and K-map them and combine the equations?

K-maps are a go to method of finding SOP/POS form for truth tables of up to 4 variables, beyond that the K-maps become explosively complex to manually draw and solve. Is it possible that for 6 bit ...
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### How to approach the highlighted part of the question?

The boolean expression for Z for the four input module came out to be A0A1A2+A0A2A3+A0A1A3+A1A2A3 I am attaching my work here.
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### Boolean Algebra Confusion

So Im going through the nand2tetris course on my own for fun, and I am at the half adder/adder portion. The half adder was pretty easy just based on the truth table, but the full adder im having more ...
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### Boolean Algebra Simplification?

So im re-learning a bit of computer architecture/boolean algebra (For the nand2tetris coursera course). Watching some videos on it one of the problems presented was: ...
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1 vote
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### Output Variable stays unintialised in my VHDL testbench

I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop. Following is the VHDL code that I have written: ...
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### Can the SOP expression be the same as POS expression?

I have a function as F(A,B,C,D)=M0+M4+M12+M8 I'm getting the simplified Product of Sum expression as C+D but I'm getting the same expression again as Sum of product
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### Reducing a given truth table with don't cares at inputs

I searched quite a bit about this but it seems not many people have a similar interest as mine regarding don't cares. Most don't care topics I found revolve around simplifying the function at hand. I ...
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### Where do Data in /Out, Write Enable, and Read Enable Wires connect to in RAM?

This is a screenshot of the Crash Course Video Registers and RAM #6. From YouTube, here's the link "Crash Course Video". It's talking about using Gated latches to store memory, and putting ...
1 vote
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### NOT gate using triodes

I can't understand the functioning of the circuit of a NOT gate using a triode (vacuum tube) and a resistance (big rectangle connected between the triode's anode and the positive power supply). For ...
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### How to limit current for this LED in circuit with a load?

I'm a newbie in electronics and just recently decided to get some deeper knowledge and try to start some projects. But it didn't take that long before I became stuck. Here's my problem. I want to ...
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1 vote
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### Why are my logic gates are exploding in TinkerCad? [closed]

Why is this happening in my logic gates?
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### Which is the preferred circuit layout? Horizontal vs. Vertical (Combinational logic)

I have 2 equivalent circuits Picture 1 (Compact, a bit messier) Picture 2 (Easier to read, less compact)
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### Building a circuit which adds 2 signed numbers

I am developing circuitry to add 2 numbers with sign.They have the form: $$b_{1}:(sign)|(absoluteval)$$ I realised that the calculation of the sign of the addition of such 2 binary numbers must be ...
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### Converting this boolean expression to NOR only expression

I was given an expression which I simplified using k-maps to obtain the following: ~WY + W~YZ + ~W~X~Z I followed along with some of the other workings people have done for converting functions, but ...
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### Is it necessary to have all variables of a boolean expression in its POS or SOP form?

For example, if we have a boolean expression, anything like: X= A′ B + CD + (A+B)′ [ACD + (BE)′ ] We know this can be CD + A'. ...
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### Full-subtractor boolean expression minimization

I'm looking at the standard full subtractor circuit and have been trying to understand how the circuit is derived/synthesized based on a web tutorial. I can follow the derivation of the truth table in ...
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### Why does NOR need one more output to the multiplexor but NAND not in ALU?

Recently, I was learning "Computer Organization and Design: The Hardware/ Software Interface" riscv 2nd Edition by "David A. Patterson" In appendix A, A-37 shows the question in &...
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### How should I proceed with implementing a multiple sequence detector FSM?

I was given the following question: Design a finite state machine (FSM), with not more than 4 states, that will detect more than one number of 1’s in the previous 3 samples. For example - ...
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### How can I improve my ladder logic diagram of a vending machine?

I am trying to create a coffee and tea machine using a ladder logic diagram. There are small, medium, and large sizes. This is where I am now: Can you give me any ideas or corrections on how to ...
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### Electrical counterpart: Logical not

I'm building a circuit where I must receive a signal from a logical not. More specifically, I'm looking for a real-life electrical circuit element/component that provides power/signal on the output ...
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### How can I convert boolean algebra to logic gates?

I have a very large boolean algebra equation that I designed in Logic Friday, but it got too complicated for it to turn into gates. Note that I am a programmer, not an electrical engineer, so please ...
1 vote
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### Automatic MCU Reset for Battery-Powered Single-Button Product

I'm designing a battery-powered product with a USB-C PD charging port and a single user button. I'd like to be able to build in a feature for recovery and re-programming where the user holds down the ...
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### How to express this logic circuit with output feedback as boolean expression?

Q1. How to express this circuit as boolean expression? It uses the output as input (feedback??) to part of the circuit. Is it a special type of circuit? Q2. How do I simplify it as Nand-only ...
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1 vote
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### How do we get a -1 in a 1-bit ALU?

In the 1-bit ALU and the table that is shown below, as you can see, the output is -1 when F0 = 1, F1 = 1, ENA = 0, ENB = 0, INVA = 1, INC = 0. The table is taken from a book (Structured Computer ...
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### Logism: Further reducing number of logic gates in a circuit

I have this circuit attached below that has an arbitrary behavior. I want to reduce the number of gates more if possible. I've taken its expression and passed it through multiple boolean expression ...
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### How do I simplify the two boolean expressions?

I have the two expressions that I have already simplified as much as possible: C̅D̅ ∨ A̅B̅D ∨ A̅BC̅ AB ∨ AC ∨ B̅C̅ However, I know that you can simplify both expressions even further per KV diagram: ...
1 vote
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### Can the output of a logic gate be split to serve as input for other logic gates?

In the textbook picture, they use 5 NOT gates, repeatedly splitting the R input only to have it go into a different NOT gate. Are you allowed to put the input of R into a single NOT gate, and split ...
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### Understanding OLD PEEL173 code

I have some code for a PEEL173 form the early 90's. I would like to understand the logic of this code, but I don't recognize this syntax. Question 1: Do you recognize the syntax of this language? What ...
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### Similarity in "carry and sum" and "difference and borrow"

i know carry and sum from all the sources i studied in YT (particularly KNOWLEDGE GATE) except neso academy that teaches using difference and borrow in same place as carry and sum Sources:- Knowledge ...
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### simplify Boolean function F(A, B, C, D) = ∑ m(0, 1, 3, 4, 5, 7,8,9 11, 13,14,15)

Hello just got stuck simplifying this boolean function using four variable K-Map. I have to simplify this boolean function in terms of sum of minterms. ...
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### Logic gate: electricity, voltage and meaning [duplicate]

I am confused by this kind of diagram (simplest, NOT gate): ------1------___Gate Here___-------0-------- Because my book tends to talk about electricity. So if I ...
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### Transition table from state truth table

Assuming a simple binary state variable allocation can be made and that any unused states can be treated as don’t cares. How would I Design a corresponding transition table for this system including ...
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### Need help determining CMOS circuits with logic function Y [closed]

I am trying to determine which of the CMOS circuits in the question below have the logic function Y, but I am having trouble understanding how to do so. I have tried looking at the circuits and ...
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### Is my simplified Boolean expression correct?

I'm trying to simplify the following Boolean expression: A'(B'C'D' + BC'D' + BCD) + A(BC'D + BC'D + BCD + BCD' + B'C'D) I've already made a few steps to simplify it, but I'm not sure if I'm on the ...
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### When given the maxterm of function, we can find its minterm of the function, which is also the complement of the maxterm,

When given the maxterm of function, we can find the minterm of the function, which is also the complement of the maxterm. When do we use one (maxterm) instead of the others (minterm/its complement)? ...
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### Duality Principle, but confused by the example

The dual of a Boolean expression can be obtained by interchanging sums and products; also interchanging 0 and 1. But the dual of xy̅ + 1 is (x' + y) · 0 ( I think) Or the dual is (x + y) · 0. Q: do ...
1 vote
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### Need help understanding why I get the logic circuit wrong

Could someone care to explain why the logic circuit for this boolean expression doesn't look like this? When I select "build circuit," on Logisim, I get a different result:
1 vote
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### Kmap and boolean equation for a function

F(A,B,C,D) = Σm(1, 2, 4, 6, 8, 10, 11, 13, 15) Here's my try of the kmap: Are my kmap and boolean equation correct for this function?
1 vote
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### How to convert SoP to NOR?

I have a logical expression: F = AB + AC + CB I know its equivalent expression via NOR: R = (A ⊽ B) ⊽ (A ⊽ C) ⊽ (C ⊽ B) It is assumed that the desired expression in NOR is unknown. I know De Morgan's ...
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### Minimizing a Boolean Expression

From a 3 variable K-map I get the following expression: BC + B!C! *!=not I know that a + a!b = a, so does this mean that BC + B!C! = B + C?
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### About DEMUX/demultiplexer: can any Boolean function be realized with the help of demultiplexers?

I know that as we OR the outputs of a DEMUX we can get a function as the first screenshot which states that an OR gate generates the one-set of the function. But can any Boolean function be realized ...
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### Where am I wrong here? I don't know why I can't get it

Question: BOOLEAN SIMPLIFICATION: Prove that F(w,x,y,z) = w’x’y’z’+w’xy’z’+ wx’y’z’+wx’y’z+ wx’yz’+w’xy’z’+ w’x’yz is equals to F(w,x,y,z) = y’z’ + wx’ My solution: F(w,x,y,z) = w’x’y’z’+w’xy’z’+ wx’y’...
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### Confusion in Duality Principle in Boolean Algebra

Maybe I have got some misconception while solving a problem. Lets a logic function, X=AB+A'C By applying duality principle, I can say that, X=(A+B)(A'+C) But I can't prove both are equal. I simplify ...
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### Implying a boolean function by using 5 NANDS only - How to implant "1" using nand?

Function: f(a,b,c,d) = b' + c' + ad + a'd' I used Karnaugh map (4x4). Received that the function is all squares except square number 7 (there it is 0). Which means: Now what is the problem? When I do ...
1 vote
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### For the 4x1 MUX shown below the Boolean Expression F(x,y,z) is [closed]

The output to a 4x1 MUX is : $Y=S_1'S_0'I_0+S_1'S_0I_1+S_1S_0'I_2+S_1S_0I_3$ My answer was : $F=A_{1}'A_{2}'x+A_{1}'A_{2}x+A_{1}A_{2}'y+A_{1}A_{2}y' \Rightarrow xyz'+xyz+y'z$ The correct answer is ...
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### A three-input NAND gate is to be used as an inverter. Which one of the following measures will achieve better results?

The two inputs not used are kept open The two inputs not used are connected to ground (0 level) The two inputs not used are connected to logic supply (1 level) None of the above I get that we can ...
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1 vote
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### Show that specific functions are correct for a race-free Moore machine

Context: The goal here is to create a Latch that holds a state. We have two inputs x1, x2 and two outputs f1, f2. When (x1, x2) = (0, 1) or (x1, x2) = (1, 0) the outputs should be the same. When the ...
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### Minimizing logic expression for two-input NAND gate implementation

I have recently been struggling with this homework problem that is requiring minimization of a logic expression to be implemented using all NAND gates. The problem requires a very small number of NAND ...