Questions tagged [boolean-algebra]

In mathematics and mathematical logic, boolean algebra is the branch of algebra in which the values of the variables are the truth values true and false, usually denoted 1 and 0 respectively. Boolean algebra is used in the analysis and simplification of digital (logic) circuits

Filter by
Sorted by
Tagged with
1
vote
1answer
48 views

Simplifying boolean equations with K-map

My professor told me that I could arrive at the simplified solution using the K-map, which I guess I did, however it does not seem correct. The equation and corresponding solution are shown in the ...
-1
votes
0answers
24 views

**How to Implement the following Boolean function using a multiplexer.** [closed]

How to Implement the following Boolean function using a multiplexer. F(A,B,C,D, E) = Sum (1, 3, 14, 16, 22, 23, 24, 27, 30)
0
votes
1answer
45 views

Optimizing Multilevel circuit Logic with SDCs

I am reading "Principles of Modern Digital Design" on chapter 3.10, but I am confused on a certain part. It says that you can reduce multilvel circuit logic using SDCs. Suppose you have the ...
0
votes
0answers
23 views

Is state machine based sequence detector easier to verify than shift register based one?

Suppose I have two versions of sequence detectors: one is based on let's say Moore machine and the other one is based on simple shift register & comparator. Which one among these is easy to verify ...
0
votes
3answers
88 views

What does the AND gate do to prevent electrical current?

I’ve been learning about Boolean algebra and I’m curious as to why 0 AND 1 is 0. In a computer’s circuit, I’m imaging 1 being electrical current flowing through the circuit, and 0 being no current is ...
1
vote
2answers
53 views

Designing a Combination Lock FSM: Converting State Diagram to Logic Gates

I am trying to design a Synchronous combination lock for my digital logic class. I have the state diagram, as I understand how to draw out the logic which I want to follow. However, I am struggling to ...
1
vote
1answer
60 views

Implementation of a logic circuit using NOR gates substituted for NAND ones

My goal is to implement logic function F = XY + ZW. In previous board, It was constructed by using three NAND gates as brought in below photo. Yet, by employing NOR gates, I have to make use of eight ...
0
votes
0answers
23 views

Needed someone to double check my boolean equation to my schematic diagram

I wrote out the boolean equations for each output but after {(AB)' +C}', I wasn't too sure if it was right. Thank you in advance. This is the truth table that I made so far if the boolean match the ...
0
votes
0answers
29 views

Convert expanded boolean function into a switching matrix

I am given a boolean function f(x) that I have to develop them according certain variables, let's call them a0 and ...
1
vote
1answer
39 views

Determine the functions of the given multiplexers

In the following problem I want to understand a section of the overall problem. The image only show 2 MUX(es), however the original question has a lot more that are ...
1
vote
1answer
59 views

SR FlipFlop Question

I am studying Digital Logic Circuit right now and I have question to ask. I have searched lot of places in order to find this answer, however due to my lack of searching ability I was not able to find ...
1
vote
2answers
50 views

adder in binary addition: XOR instead of OR gate

I am just a newbie starting out in electronics with no experience. Why do we need XOR and AND gate for the binary adder? is there any particular reason why only these two specific gates are needed ...
1
vote
2answers
83 views

Multiple Switch Equation to NAND Only equation

I'm trying to convert a regular Boolean equation that has multiple inputs into a NAND only equation. My guess is that I'm supposed to convert using DeMorgan's law, but I'm not entirely sure how to do ...
0
votes
1answer
51 views

Question On Logic Gates

In a small railway station, there are three platforms, #1, #2, #3. Up and down trains can enter in platform number #2 and #3, but platform #1 is only devoted to up trains. Design a logic circuit using ...
0
votes
1answer
38 views

How can I determine what type of logic structure this circuit represents?

I have the following circuit: How can I determine which one of the following functions it represents: F = (AB+CD)' F = ((A+B)(C+D))' F = AB+CD
0
votes
3answers
78 views

Making complex boolean circuits that give true as output only for a specific combination of boolean inputs

This is my first question on a stack exchange website so please bear with me. I am making challenges for a jeopardy style capture the flag event in my college and I had come across the minetest ...
0
votes
2answers
120 views

How to convert 8 bit binary to BCD using logical gates on multisim?

I have a task to convert analogue signal to digital on multisim. But multisim have no Ic to convert 8 bit binary to BCD. Now I have to make logic circuits to convert 8 bit binary to bcd. I have used ...
0
votes
0answers
35 views

Reducing a boolean function with NAND |

The notation \$ c|d \$ is to be read 'c NAND d' I have this function: $$f(a,b,c,d)=(a+b)*(c|d)$$ $$=(a+b)*(\overline{c*d})$$ $$=(a+b)*(\bar{c}+\bar{d})$$ $$=(a\bar{c}+a\bar{d}+b\bar{c}+b\bar{d})$$ $$=(...
0
votes
0answers
32 views

How to reduce a boolean function fast and easy?

I want to reduce the following function: $$f(a,b,c) = (\bar{a}+\bar{b}+\bar{c})*(\bar{a}+\bar{b}+c)*(\bar{a}+b+\bar{c})*(\bar{a}+b+c)*(a+\bar{b}+\bar{c})*(a+b+\bar{c})$$ Now my method would be to ...
0
votes
0answers
28 views

How do I realize the function using only 4:1 MUX and Inverters?

$$\begin{array}{ccccc} \hline \boldsymbol{a} & \boldsymbol{b} & \boldsymbol{c} & \boldsymbol{d} & \boldsymbol{f}(\boldsymbol{a}, \boldsymbol{b}, \boldsymbol{c}, \boldsymbol{d}) \\ \...
0
votes
5answers
85 views

Validation of data in electronics

Suppose, I have data which is stored in some EEPROM memory. The EEPROM is connected via an I2C interface to a microcontroller, and this microcontroller is connected to an RF receiver circuit. Assume ...
1
vote
0answers
39 views

Realizing an XOR expression using NAND gates [duplicate]

I've been trying really hard to understand the construction of a logical circuit using only NAND while also trying to minimize the number of gates. The minimization of gates is what is really ...
0
votes
0answers
22 views

Is loop made up of only don't care a prime implant?

this is four variable karnaugh map. a'bcd' ins confusing me. Is it prime implicant?
1
vote
1answer
41 views

Process function to NAND and use only negative conjunction functions

I have a system built only NAND implementing this function. I have to process this function using only De Morgan's law and finally get only negation conjuction functions. I did it but I'm not sure ...
1
vote
2answers
69 views

How to prove boolean algebra rules without truth table?

In boolean algebra I found the rules like the redundancy theorem and de morgan's law, a little unintuitive. Although the truth table shows it all, I wonder if the rules were made by experimenting ...
2
votes
1answer
64 views

Circuit to detect two sequential pulses

I have a window comparator with two outputs (hi-threshold and low-threshold) that would go high sequentially (few examples shown in the attached image). I want to use to combine these two signals into ...
0
votes
1answer
40 views

How was the result of this SOP (sum of products) expression reached?

I have a boolean expression for which I have to get the truth table and standard SOP expression without using a Karnaugh map. Here is what I got: I do have the final answer of the SOP expression, ...
1
vote
1answer
74 views

Is A XNOR B logically equivalent to A XOR (NOT B)?

I am just wondering if its fair to say that A XNOR B is logically equivalent to A XOR ~B? If yes, how do I justify that without a truth table?
0
votes
1answer
54 views

How do I get the output of this circuit?

I am trying to solve the truth table of the following circuit: A, B, and C are the inputs. I tried getting the truth table by drawing the circuit in an online circuit simulator such as falstad.com/...
0
votes
1answer
36 views

Toggle between Half-adder and Half-subtractor

I have constructed a half-adder that looks like this: And a half-subtractor like this: It's basically the same circuit except the AND gate at the bottom has a NOT ...
-1
votes
2answers
73 views

Possible to build and OR gate out of only AND/NOT?

Is it possible to construct an OR gate from only a combination of a NOT and an AND gate? Or ...
0
votes
0answers
21 views

boolean algebra for a D Latch

I am trying to understand the boolean algebra for what X and Y equals for the D Latch below. By just looking at the circuits and the NAND gates I was thinking that: $$X = (Y * (A*B)')' = (Y * (A' + B'...
0
votes
0answers
30 views

Formally determining the minimum number of poles needed to realize some suggested switching arrangement

Many times, when designing passive switching circuits, one has the following engineering problem: We know we want to have some number of switches, each with some number of throws. For each possible ...
0
votes
3answers
177 views

Design a combinational circuit with two inputs and four outputs. The output binary number should be the square of the input binary number

I don't know how the output expression for each output produced from the truth table. Can someone please explain how this output expression was dervied from the truth table? Problem: Design a ...
0
votes
1answer
94 views

Converting SOP to POS form

The boolean function I want to convert is: F = xy' + yz' I will first convert it to canonical form: F = xy' + yz' ------> (1) = xy'(z + z') + (x + x')yz' = xy'z + xy'z' + xyz' + x'yz' = Σ(2, 4, 5,...
2
votes
0answers
46 views

Logic operation on Karnaugh Maps?

Question: Normally I find Karnaugh Map of an expression from its truth table, but can we have Logic operation on two Karnaugh Maps ? Update:
0
votes
0answers
29 views

What pattern can be assumed to write the functions of a 16x4 priority encoder?

How can we find the expressions of the solutions without using K-Map or the Tabulation method?
0
votes
1answer
66 views

Universal operator

XMN(A,B,C,D)=(A XOR B) NAND (C NOR D). Is XMN is universal operator? a. yes without constants. b. yes with 0 constant c. yes with 1 constant d. yes with OR gate. e. no. What does it means universal ...
0
votes
0answers
26 views

How to convert bdd to cnf using cudd package?

I am using cudd package to create ROBDD from given circuit. Now I am interested in converting that ROBDD in CNF form. Can we do that, anyone, who has done that?
1
vote
1answer
121 views

I have a problem with understanding the attached ALU (6 control bits)

I have an Arithmetic Logic Unit, as shown below (I also included a CircuitJS simulation of it, so it will be much easier to understand the inner working of said ALU). ‘x’ and ‘y’ are the 4-bit input ...
0
votes
1answer
50 views

Using Associativity to Reduce Number of OR Gates

EDIT: I think I'm probably more confused than I realise. My question could also be phrased as "how was the given diagram constructed from the expression, particularly with reference to the OR gates?" ...
0
votes
1answer
59 views

Remake a Circuit using Multiplexers

I made this circuit yesterday using normal logic gates and chips: $$(AB)+(A\bar BC)+(\bar AC)$$ Now I have to remake it using only MUX but Im having some trouble. From my understanding I should use ...
0
votes
1answer
51 views

Minimum number of transistors to implement cmos logic of this function

I have designed the following circuit to implement cmos logic of : \$out=\overline{(a+b).\overline{c}+e.(\overline{f}+\overline{g})}\$ I’m looking for optimal circuit with minumum number of ...
2
votes
1answer
85 views

Solving CMOS logic structures

Can somebody please help me with understanding how to derive the equation from the red box from included picture (the other equations are trivial, it's just the right usage of De'Morgan's law)? I am ...
2
votes
0answers
45 views

Determine maximum length of repetitive sequence in synchronous FSM

I have the following realisation: The figure shows a synchronous circuit with the clock on Rising Edge. The circuit will generate a sequence of values on the output (abcde) of the five D-flip-flops. ...
-3
votes
1answer
66 views

building a 3 input logic gate combination bounded by a simple if else statement

For 3 variables x,y,z and output w I need help buiding a ...
0
votes
0answers
266 views

Mapping XOR expression into K map

I know any SOP and POS can be minimised directly with the help of KMAP and there is no difficulty in mapping each Boolean product or sum term into KMAP. However what if the boolean expression is in ...
0
votes
1answer
68 views

Converting gates in XOR circuit to NAND gates

I have this XOR circuit: I tried to write it using only NAND gates and this was the furthest I got: According to my book, it should look like this: I did this: $$(x.y')+(x' . y) = ( (x. y')+(x' . y)...
0
votes
0answers
45 views

Can someone explain to be what I am supposed to do in these questions (simplifying boolean algebra)?

I'm reading Digital Design by M. Morris Mano and I am solving the exercises. I got stumped in some of the questions. In this one I am not sure how to do b). To get F I did the SOP using the truth ...
0
votes
1answer
258 views

Implementing 3 variable boolean function using mux 4 to 1 and inverter

I'm trying to understand if it's possible to Implement boolean function with 3 inputs using only mux 4 to 1 and inverter. As far as I understand I can put in the selectors the first 2 variables to ...

1
2 3 4 5
7