Questions tagged [bram]

The tag has no usage guidance.

Filter by
Sorted by
Tagged with
0
votes
0answers
26 views

Error while reading the BRAM location from PS side zynq interface

I am trying to write to BRAM from PL and read the written data from the BRAM location using zybo z7 board. But when I read the written data from PS side its not giving the correct output. The ...
2
votes
0answers
101 views

Export contents of block ram to a file in Xilinx FPGA [closed]

Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
0
votes
1answer
355 views

Why is there seemingly no delay in a block ram read

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
1
vote
1answer
3k views

What is the difference between BRAM and distributed RAM [closed]

I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?
1
vote
1answer
1k views

How to generate BRAM using vivado HLS?

I am trying to create an IP using Vivado HLS. I have a lot of arrays. I have given directives to infer BRAM, with my array bram_arr like ...
0
votes
1answer
209 views

VHDL/FPGA Should I block down an array into arrays of dimensions with powers of 2?

I'm building a VGA display with a Xilinx FPGA. I'm not exactly sure what's the best way to store VGA frames. The resolution is 640x480. Should I just use a 640x480 2D array or block 640x480 into ...
1
vote
5answers
3k views

FPGA BRAM initialization

I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
5
votes
2answers
1k views

Is this BRAM being fully utilized if I use a different data width?

Background I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. Here are some important excerpts from the document (referencing pages 11 ...