Questions tagged [bram]
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FPGA ROM to Logic Optimisation Question
I am working on porting a large modern logic IC based PCB design to FPGA. It's a personal project, not work/professional or school homework. Just a learning exercise for myself. Part of this design ...
Memory in FPGA: buffer to store bytes "sent" by SPI Slave
I asked before what SPI slave is and how the received data could be stored... SPI slave collect a byte a sent it to FIFO as a temp buffer and the next step is to send the bytes to a memory. I have ...
Using BRAM as buffer
I'm trying to implement a buffer for an image processing pipeline and need to load data into BRAM. I've been following an online tutorial (https://www.youtube.com/watch?v=n35zS__YEFQ) for implementing ...
Fastest way to search RAM
I want to search RAM for a value, does anyone know which implementation will be the fastest. Im assuming that parallel search will be required. My implementation would be to use a DeMux for each ...
Sending data to FPGA [closed]
If I send 160bit message to an FPGA using TCP/IP Do I need to store the message in BRAM first ? Not sure how the FPGA receives data and gets to work on it yet.
Read from BRAM and write into 2D array in VHDL
I have initialized a single port BRAM (clk,din,dout,addr,we) 8X10 with .coe file. I want to read from BRAM and write into the 2D array of dimension 10X8. As the dout of BRAM is 8 bit but the width of ...
How to Simulate VHDL when Using a Vendor's Tool Generated Instantiation Code?
I'm working with a Gowin FPGA and they recommend instantiating block RAM. That sounds great, but how do I simulate that? I would expect there to be a library with the model for the instantiation ...
Export contents of block ram to a file in Xilinx FPGA [closed]
Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
Why is there seemingly no delay in a block ram read
I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
What is the difference between BRAM and distributed RAM [closed]
I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?
How to generate BRAM using vivado HLS?
I am trying to create an IP using Vivado HLS. I have a lot of arrays. I have given directives to infer BRAM, with my array bram_arr like ...
VHDL/FPGA Should I block down an array into arrays of dimensions with powers of 2?
I'm building a VGA display with a Xilinx FPGA. I'm not exactly sure what's the best way to store VGA frames. The resolution is 640x480. Should I just use a 640x480 2D array or block 640x480 into ...
FPGA BRAM initialization
I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
Is this BRAM being fully utilized if I use a different data width?
Background I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. Here are some important excerpts from the document (referencing pages 11 ...