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Questions tagged [bram]

Block RAM (Random-Access Memory), commonly used in FPGAs

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Stateful logic synchronization clock with memory read/writes

I am working on a hobby project using Verilog and iCEstick evaluation board. I have a stateful logic (FSM) which needs to read and write to the on-chip block RAM. Now I am a little bit confused, it is ...
Alexandr Savochkin's user avatar
-1 votes
1 answer
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Populating BRAM using a .coe file on Xilinx Alveo U280

I am new to the world of FPGAs. I am using Xilinx Alveo U280. While performing a task in my research project, I tried to populate the BRAM with 0's but the simulation shows 'Z', 'ZZ', and 'ZZZZ' as ...
afterlifeswag04's user avatar
1 vote
1 answer
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FPGA ROM to Logic Optimisation Question

I am working on porting a large modern logic IC based PCB design to FPGA. It's a personal project, not work/professional or school homework. Just a learning exercise for myself. Part of this design ...
M1GEO's user avatar
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Memory in FPGA: buffer to store bytes "sent" by SPI Slave

I asked before what SPI slave is and how the received data could be stored... SPI slave collect a byte a sent it to FIFO as a temp buffer and the next step is to send the bytes to a memory. I have ...
LeeLeeYa's user avatar
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2 answers
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Using BRAM as buffer

I'm trying to implement a buffer for an image processing pipeline and need to load data into BRAM. I've been following an online tutorial (https://www.youtube.com/watch?v=n35zS__YEFQ) for implementing ...
OM222O's user avatar
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-2 votes
1 answer
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Fastest way to search RAM

I want to search RAM for a value, does anyone know which implementation will be the fastest. Im assuming that parallel search will be required. My implementation would be to use a DeMux for each ...
Yogi Bear's user avatar
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2 answers
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Sending data to FPGA [closed]

If I send 160bit message to an FPGA using TCP/IP Do I need to store the message in BRAM first ? Not sure how the FPGA receives data and gets to work on it yet.
Jay's user avatar
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1 vote
1 answer
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Read from BRAM and write into 2D array in VHDL

I have initialized a single port BRAM (clk,din,dout,addr,we) 8X10 with .coe file. I want to read from BRAM and write into the 2D array of dimension 10X8. As the dout of BRAM is 8 bit but the width of ...
Nupoor Katre's user avatar
1 vote
1 answer
236 views

How to Simulate VHDL when Using a Vendor's Tool Generated Instantiation Code?

I'm working with a Gowin FPGA and they recommend instantiating block RAM. That sounds great, but how do I simulate that? I would expect there to be a library with the model for the instantiation ...
gnuarm's user avatar
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Export contents of block ram to a file in Xilinx FPGA [closed]

Assume I have a simple adder Verilog code which does sum=a+b This code is implemented on a Xilinx FPGA (Basys3). At every posedge of clock, I change a and b. I get sum. I run this simulation for ...
Nanditha's user avatar
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Why is there seemingly no delay in a block ram read

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
NeilMonday's user avatar
2 votes
1 answer
12k views

What is the difference between BRAM and distributed RAM [closed]

I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?
Student's user avatar
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1 answer
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How to generate BRAM using vivado HLS?

I am trying to create an IP using Vivado HLS. I have a lot of arrays. I have given directives to infer BRAM, with my array bram_arr like ...
Gilson Varghese's user avatar
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1 answer
332 views

VHDL/FPGA Should I block down an array into arrays of dimensions with powers of 2?

I'm building a VGA display with a Xilinx FPGA. I'm not exactly sure what's the best way to store VGA frames. The resolution is 640x480. Should I just use a 640x480 2D array or block 640x480 into ...
A__A's user avatar
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5 answers
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FPGA BRAM initialization

I need to create a lot of BRAM blocks in my (Altera) design. Each one has unique memory contents, determined a priori using an algorithm. Before, I was setting a parameter for each BRAM cell to read ...
Ted X's user avatar
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6 votes
2 answers
3k views

Is this BRAM being fully utilized if I use a different data width?

Background I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. Here are some important excerpts from the document (referencing pages 11 ...
Klik's user avatar
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BRAM memory in FPGA

Can someone explain how a Block RAM in FPGA works? I was creating a memory for 128k and could not figure out how would I create a memory module for it.
cheeky's user avatar
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