Questions tagged [bus]

is a subsystem that transfers a plurality of digital bits grouped together to achieve or represent a common function or variable.

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39 views

Shared bus in FPGA (arbiter + perypherial bus) [VHDL]

I am trying to implement shared bus in my fpga design. I am thinking about something similar to the microcontroller bus. I see two possibilies: Second option is easier to implement but if bus is ...
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1k views

How does an Intel processor “talk” to an I2C device?

I don't come from an Electronics background, so please bear with me. Assume an Intel processor wants to talk to a temperature sensor over the I2C bus. How does the underlying communication look like? ...
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44 views

What is XCLR and EOC

As the title says, looking at IC9 (BMP085), could someone explain why XLCR and EOC are connected to P-XCLR/P-EOP and why there is no other match in the schematic? Are these connected at all? If not, ...
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4answers
103 views

RS422, RS485 Termination Resistors

While going through this youtube video from TI about the RS232, RS422, RS485 differences. One thing that don't understand clearly is following slide from this video. The blue resistors that I marked ...
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5answers
622 views

Does ISA bus (or PC/XT bus) have some means of arbitration to resolve bus contention?

My understanding of ISA bus is that the CPU places an address on the bus and any expansion card is free to respond to that address by taking control of the data bus. I presume that tri-state buffers ...
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1answer
44 views

Interfacing LIN bus with CAN

On the following figure, LIN is used to build subnetworks from a CAN bus: Is there any standardized way to interface these two buses (e.g. for addressing a LIN node from a CAN node)? I read an ...
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2answers
140 views

Anyone know this serial bus waveform?

I'm working decoding some house intercom devices to know when someone is calling and also be able to open the door. To do this I buffer the signal (some models has 15v, others 24v...) to a 3v3 level ...
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1answer
52 views

Why is a LIN cluster limited to 16 nodes?

It says everywhere that a LIN network can be made up of at most 16 nodes (1 master node and up to 15 slave nodes). The id field however is 6 bits long allowing for more than 15 slaves to be addressed. ...
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1answer
39 views

I2C bus arbitration - communication layer

I want to understand about the communication layer on which I2C Bus arbitration is done. My question is based on this question which was previously asked here. The accepted answer states that Bus ...
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0answers
21 views

Duplicate Net Names Element When Connecting Buses between sheets in Hierarchical Structure “Solidworks PCB”

I am using Solidworks PCB , "based on altium" I am trying to connect signals from one sheet to another using Hierarchical Structure at one sheet I connect all signals to a bus by labeling each ...
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86 views

Can you help me improve this circuit design?

I'm a electronic noobie and for a school project I need to design a circuit that will then be connected to a micro controller. The aim of the project is to build a sniffer to decode a particular ...
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1answer
59 views

One voltage regulator (varistor?) instead of dozens of current limiting resistors in an LED array?

I am trying to be smart with a breadboard that runs dozens of TTL lines together, and which are monitored with LEDs. All the chips I am using are inherently current limiting enough so I won't burn my ...
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1answer
75 views

Can a non-enumerated device conduct DMA operations?

PCIe devices can read or write to memory, i.e. can do DMA without requiring a device driver. For example: pcileech (The PCIe FPGA device is controlled by another computer). If I remember correctly, if ...
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39 views

Avoiding shorts when switching between bus lines with a mechanical switch

I've designed a circuit to choose between two 8-bit digital buses. I'm taking advantage of the fact that the 74AC540/541 chips have tristate outputs, so can enter into high impedance state to allow ...
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2answers
68 views

Buses and the ALU in the 8086

Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5): If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
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54 views

Meaning “Colay with mSATA”

In a datasheet of a embedded device (this one in my case) what does it mean that the PCIe bus is conneceted to a socket that says "Full-size Mini-PCIe (colay mSATA)"
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19 views

LSM303CTR 3-wire SPI and I2C - conceptual problem

I'm trying to interface LSM303CTR e-compass from ST-microelectronics with microcontroler. Due to design limitations I have to use 4-wire SPI. This MEMS device has option to switch beetween 3-wire ...
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2answers
76 views

What is the role of the ROOT COMPLEX in a microprocessor system (PCI Express)

I have been learning about the Linux kernel and the most common bus type i always encounter is the PCI bus. As an electronics Engineer, i decided to look at how this bus works as it seems to be the ...
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1answer
78 views

Practical considerations using Ethernet bus for a large number of sensors?

I understand that an Ethernet bus design with hubs has largely been superseded by star topologies with switches and that is largely due to the issues of collisions. However, I am interested in ...
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0answers
39 views

Powering long-distance sensor bus

I need some help with my project. I'm building an outdoor sensor network with a bus topology. Every sensor node is a 3.3V system which contains an MCU + the sensors + transceiver. For communication, ...
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1answer
71 views

How to identify 422 or 485 bus from the PCB

I have a very old CPU card, maybe 1980's. It has following chips on it and most probably these are used for communication with the rest of the system. SN55188 Quad Line Drivers SNJ55189 Quad Line ...
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1answer
105 views

KiCad Saying Pins Not-connected

So I am fairly new to using KiCad, and I have encountered a problem. I recently learned how to make hierarchical pins for bus assignments with the notation. ...
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1answer
63 views

How to understand these 8086 bus cycle timing diagrams

Please see the two diagrams below. In the first diagram, each state (T1, T2, ...) seems to begin with the clock low. In the second diagram - with the clock high. If we look at the DR/R' signal - in ...
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2answers
52 views

Data transfer from/to memory [closed]

Consider an interface (between a memory and a processor, or between a memory and an ASIC, or similar situations) in which there is a data bus of 8 bit. Suppose I want read a 16 bit data from memory, ...
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0answers
37 views

Numbered rippers versus names in schematic capture

Long-time Altium guy here that just came onto a team that uses Mentor DxDesginer. When I first came onto the team, several people warned me to be careful with rippers, because they can inadvertently ...
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1answer
28 views

Calculating Joint (Load in lbs or Kn) requirement for a compression lug on top of a bus bar

I have found myself in an interesting scenario that is actually more mechanical in nature but maybe you guys can point me in the right direction. I am having a hard time finding any ISO, IEC, or ANSI ...
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2answers
74 views

VME64 vs PCI Bus for vibrating environment

I have to select between VME64 bus and PCI bus and one of the important decision metric is concerned with the connector types used in these buses. My application is in a vibrating environment. I ...
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3answers
140 views

CAN Physical Layer With Different Characteristic Impedance

The company I have been working for, which is designing a new control system for forestry equipment, has encountered a number of problems with regards to the CAN bus it is using for communication. I ...
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2answers
81 views

Termination between driver and transceiver

I have the following line driver and line transceiver driver: 74VHC244 transceiver: 74VHC245 They're connected via a 0.5m long ribbon cable with an impedance of 100Ohm. The digital signals have a ...
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1answer
59 views

Multiplexer to switch between many sets of 8 channels [closed]

I have many (up to 16) 8-channel "buses" (not digital, but analog) each with signals which I want to read with a single 8-channel analog-to-digital converter (ADC). I would switch between these ~16 ...
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1answer
34 views

Comparator with hysteresis for bus-powered communication

I have a circuit that, supposedly, converts a current-modulation signal to a digital signal. This is basically the receiver end of a bus-powered, bi-directional serial communication device (master). ...
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1answer
25 views

Data Lines on VME64 Bus

I am learning about the VME64 bus. It has only 16-bits of data bus on its P1 connector while no data pins on P2 connector. Does it means that VME64 is actually a 16-bit bus?
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1answer
36 views

Pins for VME64 Bus arbitration

I have a board that has VME64 core implemented in it and this board communicates with other boards via VME64 bus. All boards share the same backplane motherboard which has J1, J2 connectors on it. If ...
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1answer
23 views

Bare minimum pins for VME64 Bus

I have a board on which core for VME64 bus is implemented and it communicates with other boards on VME64 bus using only 1 connector (P1, 5 rows, 32 pins on each row, total 160 pins) instead of 2 ...
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3answers
82 views

What is the difference between a multiplexed bus and a multi-master bus

The jargon of terms in bus architecture literature is half the difficulty in understanding it. At some places the term 'multiplexed' bus is used while at some other places 'multi-master' bus is used. ...
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1answer
76 views

Bus mastering VS Bus arbitration [closed]

If there are multiple bus masters possible in a bus architecture then is it certain that 'Bus arbitration' will take place before a master gets hold of the bus control or is it possible that bus ...
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1answer
102 views

CAN bus load limitations

I have to send periodic frames with high frequency on a CAN bus. When I do that, the bus load becomes more than 60%, which causes delay with the received frames. Is there a problem when using higher ...
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2answers
80 views

Lack of 'determinism' in Ethernet bus

While reading this website, I found out tha there is lack of 'determinism' in the Ethernet network bus as compared to some other buses like 1553. What I understand is that Ethernet is a single master ...
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1answer
45 views

How does the north-bridge (or analogous hardware) route memory reads and writes? [closed]

I would be tempted to think that there is some kind of parallel cache-line kind of mechanism, that works on registers that are set by the north-bridge drivers. But then, most architectures only allow ...
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1answer
144 views

Microprocessor architecture bits vs bus sizes

I am ready following on this website: "Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
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1answer
165 views

Altium - Handling Multiple net names for buses

I'm confused on how to solve this warning on Altium. ...
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1answer
76 views

CAN Problems with MCP2515, MCP2561 and Rpi

I work with some devices which used STM32 MCU and MCP2561. Theses devices talks on a CAN Bus. Everything is ok. But when i plug a Raspberry Pi with a MCP2515(Spi) and a MCP2561. I see a lot of ...
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1answer
111 views

Number of bits after stop bit before going to idle state. Is it regulated by a industrial standard?

Does anyone know a number of bits after stop bit before going to idle state. Is there any standard on this matter (e.g. industrial)? Update: So my questions are: What marked areas stand for. What ...
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78 views

Altium: Repeating SPI/I2C Blocks

What is the proper way of repeating I2C/SPI blocks? Since we know in the case of SPI blocks, MISO, MOSI & SCK must all be tied together in a single bus for communication to happen. I have read ...
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2answers
134 views

Is only a firmware limitation the fact that some camera can't store photo in RAW format? [closed]

I was interested in understanding if from the point of electrical engineering storing the RAW data of the sensor directly into the memory of the camera require special hardware. Could be more ...
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1answer
73 views

Why do we need 'R_out' in 2-BUS arch?

Given some abstract architecture of CPU: Note that this CPU has 2-BUS. Why do we need the R_out and R_in? If I use Gra/Grb/Grc then obviousely I will need R_out. The Same for R_in when I use Sra/Srb/...
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62 views

Everything seems fine, but SPI Read/Write simply doesn't work. (Hardware-related)

Made a working breadboard Made a working protoboard Printed PCB - same exact schematic and code. Having issues. It appears to be just fine. The SS lines are working from the Pi all the way to the ...
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1answer
56 views

Pullup resistor operation between the ESP32 and a Bus MCU

I have an ESP32 as my main controller and a Bus. The bus operates where Pins 55 & 56 needs to be HIGH in order for the bus to be OFF. My ESP will drive the bus by enabling it by pulling those ...
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53 views

What is the fieldbus for Unitronics PLC?

I am currently investigating the inner behavior of a PLC of the brand Unitronics. I identified several bus for the communication with actuators, other PLCs, etc (like Modbus or CANbus) One thing I ...
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0answers
21 views

Isolation of SD IO pins during off state

I have a project at the moment that uses a PMOSFET to switch the supply to an SD card. According to the SanDisk SD datasheet available here: Because there are clamping diodes on the CMD, CLK, and ...