Questions tagged [cache]

Cache is a type of memory used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.

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Cache Memory Read and Write Miss/hit policies: details of a real processor

All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
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How x86-64 Intel CPU understands how many bytes load into a register

I have the following byte code one the left and and its byte representation on the right: ...
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Is cache the same as ram [closed]

is L1 cache and L2 cache your computers Ram? My Performance stat in task manager says L1 224kb and L2 says 4mb? Tried reading other posts but were too complicated to understand.
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CPU cache write policy - evict already dirty? + storage of memory address

I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear. Also, a write to a main memory location that is not yet mapped in a write-back ...
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How would I go about the write port of a set-associative cache memory?

Let's consider a four-way set-associative cache, just like this one: As you can see this cache has a read port but there is no write port. I was wondering if you guys could help me figure out how one ...
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How to use two Demux to index a matrix layout of registers

Consider the following. Let's say for simplicity sake I have an arrangement of 8 bit registers in a 4x4 matrix layout. I could easily use a Demux that has a 4 bit input select line for the addresses ...
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How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?

I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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What information exactly does an instruction cache store?

Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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Cache miss types: capacity miss vs. conflict miss

Categorizing Cache Misses I was wondering if somebody could provide an example illustrating a capacity miss in contrast to a conflict miss for a 2-way cache with arbitrarily small line size and cache ...
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CPU Memory Hierarchy: Calculating Average Memory Access Time

(From Schuam's Outlines Computer Architecture, 2002, page 193, problem 8.7(b)) Suppose I have the following memory hierarchy of: CPU <-> SRAM <=> DRAM <=> DISK SRAM has 5 ns access time ...
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Multilevel cache effective access time calculations considering cache miss

I was solving exercise from William Stallings book on Cache memory chapter. The problem was: For a system with two levels of cache, define Tc1 = first-level cache access time; Tc2 = second-level ...
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Cache access time for write back and write through caches

I was solving exercise questions on caching from the book Computer Organization and Architecture by William Stallings. The exercise has following question: The performance of a single-level cache ...
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How is CAM implemented?

I have a book statement: A content addressable memory is a circuit that combines comparison and storage in a single device. I want to know how this is implemented in real world? Sounds like an ...
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Cache programming techniques

I am trying to understand hardware Caches. I have some understanding, and I would like to ask if my understanding is correct. I understand that there are three types of cache mapping; direct, full ...
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Why increasing block sizes in caches leads to decreased miss rate?

My book about computer organization said that: If size of a block is 1 word (4 bytes), it will encounter 10 misses when accessing 10 consecutive integers in an array. If we set the size of a block ...
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What is the meaning of this line? “Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with 4-way associativity.”

Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with 4-way associativity. Does it mean that my external QSPI Flash is only 32Kb or it has been memory mapped onto ...
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Cache memory on hit, no data stored

So, I have a question about the cache memory, i know that if the tag matches the data will be retrieved, but what happens if the current address has the same tag with others but in that place, in my ...
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What determines the maximum size of a cpu cache?

Looking at a list of the very latest CPUs, I see several of them with a cache size of 12MB or 8MB - pretty small, when compared to the ever-increasing size of hard drives and ram. It seems to be taken ...
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Is my cache hit rate calculation correct?

I study cache memories. I'm supposed to calculate the data hit rate for a function call with a 1024 byte direct mapped data cache and block size 16 byte. ...
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Instruction cache's purpose

A processor is working at 100 MHz. The program memory interfaced to it can work only at 25 MHz maximum. Is there anyway we can fetch an instruction from it in one clock cycle of the processor ? I read ...
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Instruction Register Size in Processors

I am learning processor basics. I have this doubt. If I have a processor with 9 one-byte instructions and one 2-bytes instruction in its instruction set architecture, should n't the instruction ...
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How can cache be that fast?

Here is a screenshot of a cache benchmark: In the benchmark the L1 cache read speed is about 186 GB/s, with the latency being about 3-4 clock cycles. How is such a speed even achieved? Consider the ...
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Pipelining vs Caching in an FPGA design

To my understanding both pipelining and caching make use of memory to reduce the amount of idle hardware. I am considdering a project that has multiple input data streams with a slow clock rate, ...
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Does cache access time scale down with frequency in modern CPUs?

I have an application where I suspect the main overhead is accessing L3 cache. It is run on a modern Intel server-grade microprocessor with a huge L3 cache. There are many microprocessors available ...
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Methods to detect errors in cache

Are there methods apart from ECC, to detect and possibly correct cache errors?
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Can a CPU function with nothing more than a power supply and a ROM, using only the internal cache as RAM?

Can a CPU (such as the Intel i3/i5/i7/Xeon) with on-chip cache RAM use that as its only functional RAM, without any external memory banks attached? Or must there be external RAM, and the cache cannot ...
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Cache memory calculation

I'm learning the logic of cache memories. I wonder if you can verify that I understood correctly. If a cache memory in the tag field has 16 bits, the set field has 10 bits and the byte in block field ...
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cache memory capacity and words in cache memory

Each block of the set associative cache memory has capacity of 4 words of 16-bits, one section has 2 blocks. Whole cache memory has 4096 words. I do not understand the differences between these bold ...
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How much of a CPU die surface is taken by cache memory in modern microprocessors?

I am interested in how much of the surface of a modern or older CPU's are taken by cache memory ? Are there any statistics regarding the size that cache memory takes in CPU dies of today ? Are the ...
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12 to 6 look up table

I have an application where 12 input bits need to generate 6 output bits in a user configurable manner. Of course this requires using a RAM based look up table. I've noticed that the fastest static ...
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Which cache type is better for bus watching?

I am studying for an exam about memory (mostly cache) and I ran across a multiple-choice question from a few years back: ...
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Time average for two caches , cpu and ram

I have a CPU, with two caches, L1 and L2, with access time T1 and T2 respectively. and The time to access RAM is Tm. The hit ratio for L1 is a, and the hit ratio for L2 is b. Is the mathematical type ...
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Power consumption related to cache hit rate

Studying computer science engineering, I came across this question: We place an L0 cache in front of an L1 cache (so a fraction of the cache accesses are serviced by the L0 cache instead of the ...
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Page table - I don't understand how this table has been made [closed]

CPU has generated this sequence of logic addresses (in decimal): 777, 2047, 1199, 1100, 546, 129, 3201 page size is 512 Byte, ...
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Cache memory vs shadow RAM

I know that cache memory is much faster than typical RAMs. Apart from that, what exactly is the difference between Cache memory and shadow RAM? Both of them will have data that are to be accessed ...
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Is cache memory unnecessary in microcontrollers?

Do we use cache memory in microcontrollers, if not, why not? If yes, what is its application in embedded systems or it is enough just to have RAM?
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How do you calculate Byte Offset?

I am confused by the concept of byte offset. In my textbook the examples always show the word aligned byte offset as being two bits but doesn't really explain how they arrive at that value. It says ...
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direct mapping cache question

I have been doing the question below in what I thought was the correct way. After doing some more reading I am now slightly confused and would appreciate some clarification. Previously I was just ...
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CPU ports and cache controllers

I have seen CPUs conforming to Harvard architecture with dedicated ports for program memory and data memory. I have also seen that instruction and data caches (read-through caches) are connected to ...
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Is there a wire (a bus), albeit a very short one, between the CPU and its level-1 cache?

I was wondering what is the specific connection mechanism between the CPU and its level-1 cache so that in practice level-1 cache access time is reduced to match the CPU clock frequency? Do level-1 ...
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how to calculate CPI?

The miss rate in the instruction and data cache is 3% .A processor has a base CPI of 1.5 when all references hit the cache and a clock rate of 4 GHz. The time to access main memory is 50 ns ...
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find cache hit rate for direct mapped cache memory

I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is I currently have an 8 block main memory with 2 ...
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Increasing cache line size when cache and RAM don't work asynchrounsly

I want to improve a processor design. It has a simple directly mapped cache, and I want to improve the hit rate. I've been working on increasing the cache line size from one data word to four, but ...
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Improving a processor design in VHDL

For a project at my university we have to improve the design of a processor (more specifically, the Plasma CPU. The design is generated based on a description written in VHDL. We have to identify ...
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What are the meanings of the fields of this cache memory?

I have a cache memory simulator with this cache memory shown. The cache size is 64 bytes and the block size is 8 bytes. What is the decomposition into fields? If block size is 8 bytes, then log(2^3)=...
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What are the bits for this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant bit)....
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Which are the spec bits in this cache?

I have a direct mapped cache of size S with the line size L. The cache is physically indexed and tagged. The physical address is 50 bits, numbered from 0 to 49 (with 0 being the least significant bit)....
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How does CPU read data from the RAM?

In a general purpose computer(like normal pc), how does the CPU read the RAM, assuming that it first reads from the ...
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How much energy does cache memory consume in a modern processor? [closed]

What fraction (on average or range) of total processor energy consumption does the cache subsystem consume in modern processors (say post 2009)?
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How do I get the index of these word addresses? [closed]

We are given 32 bit memory address references. For example: 180, 43,2. We are asked to find the index "given a direct-mapped cache with two-word blocks and a total size of 8 blocks". Mind you have ...