Questions tagged [cache]
Cache is a type of memory used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
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Number of read and write ports on L2 and L3 cache
I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
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In Directed-mapped cache, a problem in exercise!
5.2 Caches are important to providing a high-performance memory hierarchy
to processors. Below is a list of 32-bit memory address references, given as word
addresses.
3, 180, 43, 2, 191, 88, ...
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Cache access time for write back and write through caches
I was solving exercise questions on caching from the book Computer Organization and Architecture by William Stallings. The exercise has following question:
The performance of a single-level cache ...
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In a N-way associative cache, how do we decide which "Way" to select?
I am having a hard time understanding the part of the cache after a Word has been selected by the 8:1 MUX. As far as I understand, the 2:1 MUX must have a select line coming from the MSB of the Index. ...
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How to handle flash write/read operations on STM32L552 with ICACHE enabled without disabling it?
I am currently working with an STM32L552 microcontroller and encountering some peculiar behavior when writing and reading double words to and from the flash memory. After writing data to a specific ...
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Data coherency with DMA and I2S audio on STM32H7
Moving from a audio effect prototype based on the STM32F407 to the STM32H757. Did a lot of stuff on the F4 with audio but on the H7 I'm getting stuck and can't get a simple audio loopback with DMA. I'...
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
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How different layers of cache connect in hardware?
I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:
Does the unified L2 Cache have dual port ...
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How does cache coherency and DMA work together?
I am currently reading about caches and how they are used in Computer Science. The explanation of how the cache is always up to date with the actual memory is understandable as long writing and ...
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What is the meaning of this line? "Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with 4-way associativity."
Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with
4-way associativity.
Does it mean that my external QSPI Flash is only 32Kb or it has been memory mapped onto ...
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How do computer memories interact with each other (registers, cache, RAM, ROM)?
After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
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Cache miss types: capacity miss vs. conflict miss
Categorizing Cache Misses
I was wondering if somebody could provide an example illustrating a capacity miss in contrast to a conflict miss for a 2-way cache with arbitrarily small line size and cache ...
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How does CPU control implement pipeline stall [closed]
The original question was deemed lack of focus. This post is specifically about cpu pipeline stall.
How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
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How can an instruction be fetched every cycle?
From what I understand, in a pipelined CPU, every stage takes 1 cycle. But instructions are fetched from memory which takes up to ~150 cycles. The CPU fetches most instructions from the L1-cache, but ...
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Size of a memory cache
Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.
Should ...
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Determining physical address for logical address
I have a simple segmentation system with the following segment table:
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Physical address vs virtual address
Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
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Cache comparator usage
Referring to the photo below, in direct-mapping cache design, why we need a comparator to compare between the tag in the address and the tag in the cache?
Isn't a valid bit enough?
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Debugging Cortex-M7 with data cache
I'm using gdb, openocd and stlink to debug an application running on STM32H7. When data ...
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How to find Base CPU Time and Memory-Stall Time
The program described below runs on a multiple issue processor with a 3-level CPU cache, a 4 GHz clock frequency, and the following performance metrics:
Miss Penalty R/W
Data Miss Rate
Instruction ...
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Displacement strategy for (Computer) Cache
Here, under displacement strategies, the following is written (Unfortunately, only in German available):
Laszlo Belady's method of displacing the memory area that will not be
accessed for the longest ...
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Lines transferred from main memory to Cache
I'm studying Cache memories and I would like to know exactly how the lines are transferred from memory to cache.
Supposing I have a 32-bit machine with a 16kB directly mapped cache and 8 words per ...
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Does a processor ‘know’ that there is a cache in the computer system?
I think with general purpose processors it would just go straight to the memory (let me know if I'm wrong), and the processor won't be bothered if or not there is a cache. What happens with DSPs?
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cache memory capacity and words in cache memory
Each block of the set associative cache memory has capacity of 4 words of 16-bits, one section has 2 blocks. Whole cache memory has 4096 words.
I do not understand the differences between these bold ...
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Increasing cache line size when cache and RAM don't work asynchrounsly
I want to improve a processor design. It has a simple directly mapped cache, and I want to improve the hit rate. I've been working on increasing the cache line size from one data word to four, but ...
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Do official transistor counts include cache?
Title says it all: do official transistor counts, such as here, include the transistors needed to implement L1, L2, and L3 cache? I assume they do.
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How can cache be that fast?
Here is a screenshot of a cache benchmark:
In the benchmark the L1 cache read speed is about 186 GB/s, with the latency being about 3-4 clock cycles. How is such a speed even achieved?
Consider the ...
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How x86-64 Intel CPU understands how many bytes load into a register
I have the following byte code one the left and and its byte representation on the right:
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A problem dealing with a two-way set-associative cache
This is Problem 13-4 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I did the problem. I would like somebody to confirm that my answer is correct or tell ...
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A Problem dealing with Cache memory on a computer
This is Problem 13-3 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I believe I have the answer right for part a and part b. That is, they match the ...
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Cache Memory Read and Write Miss/hit policies: details of a real processor
All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
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CPU cache write policy - evict already dirty? + storage of memory address
I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear.
Also, a write to a main memory location that is not yet mapped in a write-back ...
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How would I go about the write port of a set-associative cache memory?
Let's consider a four-way set-associative cache, just like this one:
As you can see this cache has a read port but there is no write port. I was wondering if you guys could help me figure out how one ...
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How to use two Demux to index a matrix layout of registers
Consider the following. Let's say for simplicity sake I have an arrangement of 8 bit registers in a 4x4 matrix layout. I could easily use a Demux that has a 4 bit input select line for the addresses ...
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How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?
I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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What information exactly does an instruction cache store?
Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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CPU Memory Hierarchy: Calculating Average Memory Access Time
(From Schuam's Outlines Computer Architecture, 2002, page 193, problem 8.7(b))
Suppose I have the following memory hierarchy of:
CPU <-> SRAM <=> DRAM <=> DISK
SRAM has 5 ns access time
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Multilevel cache effective access time calculations considering cache miss
I was solving exercise from William Stallings book on Cache memory chapter. The problem was:
For a system with two levels of cache, define Tc1 = first-level cache access time; Tc2 = second-level ...
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How is CAM implemented?
I have a book statement:
A content addressable memory is a circuit that combines comparison and storage in a single device.
I want to know how this is implemented in real world? Sounds like an ...
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Cache programming techniques
I am trying to understand hardware Caches. I have some understanding, and I would like to ask if my understanding is correct.
I understand that there are three types of cache mapping; direct, full ...
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Why increasing block sizes in caches leads to decreased miss rate?
My book about computer organization said that:
If size of a block is 1 word (4 bytes), it will encounter 10 misses when accessing 10 consecutive integers in an array.
If we set the size of a block ...
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Calculate Paging System
I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it.
A paging system has the following parameters: 2^32 bytes of physical memory; page size of 2^...
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Which cache type is better for bus watching?
I am studying for an exam about memory (mostly cache) and I ran across a multiple-choice question from a few years back:
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Cache memory on hit, no data stored
So, I have a question about the cache memory, i know that if the tag matches the data will be retrieved, but what happens if the current address has the same tag with others but in that place, in my ...
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Time average for two caches , cpu and ram
I have a CPU, with two caches, L1 and L2, with access time T1 and T2 respectively.
and The time to access RAM is Tm.
The hit ratio for L1 is a, and the hit ratio for L2 is b.
Is the mathematical type ...
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What determines the maximum size of a cpu cache?
Looking at a list of the very latest CPUs, I see several of them with a cache size of 12MB or 8MB - pretty small, when compared to the ever-increasing size of hard drives and ram. It seems to be taken ...
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How do you calculate Byte Offset?
I am confused by the concept of byte offset.
In my textbook the examples always show the word aligned byte offset as being two bits but doesn't really explain how they arrive at that value. It says ...
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Is my cache hit rate calculation correct?
I study cache memories. I'm supposed to calculate the data hit rate for a function call with a 1024 byte direct mapped data cache and block size 16 byte.
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Can a CPU function with nothing more than a power supply and a ROM, using only the internal cache as RAM?
Can a CPU (such as the Intel i3/i5/i7/Xeon) with on-chip cache RAM use that as its only functional RAM, without any external memory banks attached?
Or must there be external RAM, and the cache cannot ...