Questions tagged [cache]
Cache is a type of memory used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.
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Can a CPU function with nothing more than a power supply and a ROM, using only the internal cache as RAM?
Can a CPU (such as the Intel i3/i5/i7/Xeon) with on-chip cache RAM use that as its only functional RAM, without any external memory banks attached?
Or must there be external RAM, and the cache cannot ...
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How can cache be that fast?
Here is a screenshot of a cache benchmark:
In the benchmark the L1 cache read speed is about 186 GB/s, with the latency being about 3-4 clock cycles. How is such a speed even achieved?
Consider the ...
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Are page table walks cached?
On a microprocessor with hardware TLB management (say an Intel x86-64) if a TLB miss occurs and the processor is walking the page table, are these (off-chip) memory accesses going through the cache ...
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Why is L1 cache faster than L2 cache?
I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and ...
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Is there a correspondence between cache size and access latency?
Is there is a correspondence between cache sizes and access latency? All other things being equal, does a larger cache operate slower? If so, why? How much slower?
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What information exactly does an instruction cache store?
Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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stack cache instead of registers
Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is ...
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What is the meaning of this line? "Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with 4-way associativity."
Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with
4-way associativity.
Does it mean that my external QSPI Flash is only 32Kb or it has been memory mapped onto ...
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How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
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Difference between 2-way and 4-way caches?
I don't fully understand this picture:
If the data and instruction caches are separated, doesn't that mean that this CPU is not von Neumann model but Harvard model?
And what does it mean that one ...
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Sorting of data from instructions ( ARM I-cache and D-cache )
Some ARM cores like the ARM9 family of cores have a Harvard Architecture, at least at the cache level. That is they access two seperate caches, an I-cache for instructions and a D-cache for data ( ...
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Why do we need the MOESI/MESIF protocols?
As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line.
But, in the MESI protocol, only one ...
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Processor - L1 Data cache interface
Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer:
I'm ...
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Controller Resets after Enabling Cache
I am using a MCF5253 controller which is based on Coldfire Architecture.
It has 8KB of Instruction Cache.
Everything was working fine till I enabled it's Instruction Cache.
Now what's happening is ...
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I know why DRAM is slower to write than to read, but why is the L1 & L2 cache RAM slower to write?
DRAM is slower to write than read because it takes time to either charge or discharge a DRAM memory cell. But what about the SRAM in my processor's L1 and L2 caches? It's slower to write as well but ...
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Fully Associative cache offset bits
When dealing with a fully associative cache, why is it necessary to use an offset (or word), if the entire cache is being searched anyway what will the offset do for you?
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Virtual Memory, Cache, and TLB's
I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question.
I'm trying to study for an exam ...
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How many bits are used for the tag, block, and offset fields for the representation of a memory address?
A small byte-addressable embedded computer system, with a word length
of 32 bits, has a main memory consisting of 4 KBytes. It also has a
small data cache capable of holding eight 32-bit words, ...
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Instruction cache's purpose
A processor is working at 100 MHz. The program memory interfaced to it can work only at 25 MHz maximum. Is there anyway we can fetch an instruction from it in one clock cycle of the processor ? I read ...
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Cache miss types: capacity miss vs. conflict miss
Categorizing Cache Misses
I was wondering if somebody could provide an example illustrating a capacity miss in contrast to a conflict miss for a 2-way cache with arbitrarily small line size and cache ...
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Cache. MESI protocol for multilevel cache in Intel processors
Now I'm trying to simulate the performance of Intel CORE 2 Duo processor (but I'll be very pleased with information about any other multi-core Intel processor) and it's work with the computer memory. ...
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Is cache memory unnecessary in microcontrollers?
Do we use cache memory in microcontrollers, if not, why not? If yes, what is its application in embedded systems or it is enough just to have RAM?
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What determines the maximum size of a cpu cache?
Looking at a list of the very latest CPUs, I see several of them with a cache size of 12MB or 8MB - pretty small, when compared to the ever-increasing size of hard drives and ram. It seems to be taken ...
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Verilog asynchronous reads of regs - and design question
I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into:
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How much energy does cache memory consume in a modern processor? [closed]
What fraction (on average or range) of total processor energy consumption does the cache subsystem consume in modern processors (say post 2009)?
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How does CPU read data from the RAM?
In a general purpose computer(like normal pc), how does the CPU read the RAM, assuming that it first reads from the ...
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Determining physical address for logical address
I have a simple segmentation system with the following segment table:
...
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Size of a memory cache
Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.
Should ...
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How does cache coherency and DMA work together?
I am currently reading about caches and how they are used in Computer Science. The explanation of how the cache is always up to date with the actual memory is understandable as long writing and ...
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Three way set associative cache with LRU replacement
So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...
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How would I go about the write port of a set-associative cache memory?
Let's consider a four-way set-associative cache, just like this one:
As you can see this cache has a read port but there is no write port. I was wondering if you guys could help me figure out how one ...
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Time average for two caches , cpu and ram
I have a CPU, with two caches, L1 and L2, with access time T1 and T2 respectively.
and The time to access RAM is Tm.
The hit ratio for L1 is a, and the hit ratio for L2 is b.
Is the mathematical type ...
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Improving a processor design in VHDL
For a project at my university we have to improve the design of a processor (more specifically, the Plasma CPU. The design is generated based on a description written in VHDL.
We have to identify ...
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How to calculate index and tag fields lengths for a cpu cache?
I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
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What CPUs use a skewed associative cache?
What CPUs use a skewed associative cache?
I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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Cache write/read times?
I would like to devise certain rules of thumb to help solve certain computer design/architecture challenges. Hence, in memory, which operations typically take longer to execute: loads or stores?? I ...
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How much of a CPU die surface is taken by cache memory in modern microprocessors?
I am interested in how much of the surface of a modern or older CPU's are taken by cache memory ?
Are there any statistics regarding the size that cache memory takes in CPU dies of today ?
Are the ...
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Increasing cache line size when cache and RAM don't work asynchrounsly
I want to improve a processor design. It has a simple directly mapped cache, and I want to improve the hit rate. I've been working on increasing the cache line size from one data word to four, but ...
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Why increasing block sizes in caches leads to decreased miss rate?
My book about computer organization said that:
If size of a block is 1 word (4 bytes), it will encounter 10 misses when accessing 10 consecutive integers in an array.
If we set the size of a block ...
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Cache memory vs shadow RAM
I know that cache memory is much faster than typical RAMs. Apart from that, what exactly is the difference between Cache memory and shadow RAM? Both of them will have data that are to be accessed ...
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Why does small cache memory take less time to index
I was going though these slides (page 3) which are adapted from Computer Architecture: A Quantitative Approach, 4th Edition by Patterson and Hennessey.
The topic is about Advanced Cache ...
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Physical address vs virtual address
Physical address is hardware address of physical memory and virtual address is the one the processor will be seeing, it has it has a tag and offset. I understand this. Can any one describe it with an ...
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Calculate Paging System
I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it.
A paging system has the following parameters: 2^32 bytes of physical memory; page size of 2^...
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Instruction Register Size in Processors
I am learning processor basics. I have this doubt.
If I have a processor with 9 one-byte instructions and one 2-bytes instruction in its instruction set architecture, should n't the instruction ...
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unable to understand write policy in Cache memory
I am studying write policies in cache memory ( for first time ). I am able to understand the 'write-through' but i am not able to understand 'write back' and the problems associated with it . Please ...
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Please explain the details of cache circuit addressing
My cache can have 32 address bits with 2 bits for index and 3 bits for byte-offset.
Associativity 2, block size 8.
Of course, the the bits for index says which row of the cache the data is.
But ...
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Data coherency with DMA and I2S audio on STM32H7
Moving from a audio effect prototype based on the STM32F407 to the STM32H757. Did a lot of stuff on the F4 with audio but on the H7 I'm getting stuck and can't get a simple audio loopback with DMA. I'...
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Is my cache hit rate calculation correct?
I study cache memories. I'm supposed to calculate the data hit rate for a function call with a 1024 byte direct mapped data cache and block size 16 byte.
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Does cache access time scale down with frequency in modern CPUs?
I have an application where I suspect the main overhead is accessing L3 cache. It is run on a modern Intel server-grade microprocessor with a huge L3 cache. There are many microprocessors available ...
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Cache memory calculation
I'm learning the logic of cache memories. I wonder if you can verify that I understood correctly. If a cache memory in the tag field has 16 bits, the set field has 10 bits and the byte in block field ...
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