Questions tagged [cadence]

For anything related to Cadence: EDA Tools and IP for System Design Enablement

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Mutually coupled inductor modelling in cadence

I used two methods to model two mutually coupled coils. Method: 1) Using 'mind' cell from analogLib. It basically lets you define a coupling coefficient k value. Method:2) Using 'Xfmr' cell from ...
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11 views

Poly density issues in differential pair layout

I have designed layout for differential pair in 10*10um2 of area. I have used dummies and guard ring around the differential pair to avoid PVT variation. here while running the DRC(Design Rule Check)...
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52 views

Logic Synthesizer generates bad timings

I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
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27 views

What are MGT pins used for in fpga and what devices can they be connected to? How can I connect them on fgpa system planner?

Basically, I want to know the how to connect the MGT pins of fpga to any device. And which devices can I connect it to. I am working on fpga system planner.
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83 views

Why do MoM capacitors need bulk connection?

In recent am doing layout of crtmom in 180nm technology node. I found the bulk connection to MOM capacitor. I dont understand the why MOM cap need bulk connection or bulk terminal in design. usually ...
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33 views

MOSFET in cadence is symmetric? Source and drain don't really matter diagramatically

I am doing an OTA in cadence and I accidentally was using an upside down NMOS MOSFET. What I mean by that is that considering lower voltages are on the bottom of your circuit, then the arrow that goes ...
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32 views

Finding the saturation current and the thermal voltage in Cadence Virtuoso

Is there a way to find the saturation current variation from -40 to 125 in Cadence Virtuoso? I am interested to see if it is proportional to the absolute temperature or complementary to the absolute ...
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123 views

How to find un*Cox from Cadence Virtuoso?

Suppose we are posed with a problem statement saying to design a CS amplifier with specific gain. How do I design,or how do I get to know the value of gm,un,cox of the mos technology i am using. P.S: ...
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23 views

Higher order effects of CTAT and PTAT when testing a BANDGAP

I want to use candence to simulate the real behavior of a voltage reference and so far I found circuits that are based on the ideal models. What non linearities can I introduce in this ideal model ...
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3answers
56 views

Arranging multiple board files in single board file

I am going for PCB array manufacturing in order to save some costs. I have totally designed 3 different board files and I want to combine each of them side by side. Can somebody tell me the steps in ...
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1answer
124 views

sdf generation using prime time

I have a stdcell library which has “.v” file which contains all Verilog RTL models for stdcells. This stdcell library also has a “.lib” and ".db" timing files with all the delay information for these ...
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32 views

Simulation of the injected noise to oscillator in Virtuoso

I have a differential LNA that injects current to an oscillator. I want to see the thermal noise injected to the oscillator. This noise is composed of the noise of oscillator + noise of the LNA. Now ...
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1answer
122 views

Question about fingering

I have designed a circuit in Cadence Virtuoso. As a first step, I used all the transistors without fingers (i.e. each transistor is a single transistor). Once the circuit satisfied all the ...
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1answer
168 views

Phase margin is 90 degrees but transient step response shows overshoot

The bode plot of the loop is as shown here The transient step response looks like this The block diagram looks something like this - Basically a single stage opamp(OPAMP in fig) with high gain(...
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1answer
26 views

What does the layer structures and the macro structre describe in a LEF file?

I want to know what is the exact format of a LEF file. For example, I have the following format of LEF file ... I want to know what the layer and macro structures describe. Also, how many layer and ...
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2answers
159 views

What tool produces this type of layout?

I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442 Alternate link for the ...
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88 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
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66 views

How do I fix an error message “expecting an expression or operand” when reading an input file in cadence vhdl?

How do I fix the following error message? ...
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1answer
62 views

Plotting G(t) of an oscillator in Cadence

I have a cross-coupled NMOS-only oscillator that has its bias voltage changing so its transconductance is also changing over time. I want to plot its transconductance (G(t)=G0-gm/2) over time in ...
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52 views

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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1answer
51 views

Peaks in XOR-XNOR Waveforms

I have been designing some two input XOR-XNOR circuits using Cadence Virtuoso. All of them are working as expected but there is a little problem when both the inputs make a transition; the XOR and ...
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1answer
27 views

common source pole calculation vs. simulation

I would like to compare my pole simulation results to my hand calculations, I'm receiving quite a big error. when simulating a Common Source stage without output capacitance load there is a big ...
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1answer
307 views

Dynamic phase Routing In Allegro

My doubt is regarding the dynamic phase control while routing differential pairs in allegro. If anyone knows kindly clear my doubts on these questions. For your reference, I have attached a snapshot ...
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51 views

Anneal Placement

I'm doing a practice assignment, and I cant seem to understand this question. They give 6 gates in a small 6x6 grid. Each gate is drawn as a circle with number. There are 4 nets, labeled A, B, C and ...
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1answer
106 views

Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
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82 views

How to simulate under skewed process corners (SF, FS, SFA, FSA) in Cadence 65nm?

I'm testing a circuit under different process corners and I already know how to simulate under FF, SS and TT process corners. However, I'm getting inconsistent results in the skewed corners (SF, FS, ...
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77 views

Liberate - Custom Cell Characterization

Tools and Tech: ST 65nm | LIBERATE Library Characterization Platform (x86_64) 12.1.4 (altos 121) | Cadence Virtuoso 6.1.5-64b | Calibre Interactive - PEX v2012.4_16.11 I am trying to characterize a ...
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1answer
280 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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1answer
54 views

How to Reconfigure a Current Sense Amplifier Pspice Model

I downloaded the .lib Spice library for the MAX4172 and imported it into OrCad, available from: https://www.maximintegrated.com/en/products/analog/amplifiers/MAX4172.html/tb_tab2 The library file ...
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2answers
319 views

Does the capacitance values matter in a full wave voltage doubler?

I've simulated the following schematic on Cadence, and another less professional simulator called 'everycircuit'. I initially had a C1 = C2 = 10uF which simulated correctly on both simulators. Then I ...
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1answer
71 views

PSPICE graphs work separately for subcircuits, wrong when combined?

I'm working on a pulse generation circuit that will be used to drive an ultrasonic transducer. The following circuit is giving an unexpected output. It might look complicated, but really it can be ...
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2answers
129 views

Is Cadence unable to simulate AC to DC converters using simple full bridge rectifier?

I've tried several different topologies, such as the full bridge rectifier and the following which I've successfully tested on other simulators. However, on Cadence I always end up getting static ...
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1answer
49 views

Why does AC/Sweep in Cadence always require a starting and stopping frequency?

It seems as if there is no way to simply test a circuit with an AC voltage source at a single frequency. How does someone test a circuit that plugs into the main voltage at 60Hz? Is it really ...
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1answer
134 views

Using PSPICE model of gate-driver from manufacturer

I have found a PSPICE model for a part I'm interested in. ISL55110 Datasheet: https://www.mouser.com/datasheet/2/698/isl55110-11-1302115.pdf Manufacturer PSPICE Model: https://www.renesas.com/cn/zh/...
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1answer
140 views

PSPICE simulation of capacitor voltage and current disagrees with math

I'm testing a simple enough circuit on PSPICE. The zener has a BV = 220V, so the capacitor has a voltage of 220V until the switch closes. Using the time equation for voltage of a capacitor: Vc(t) = ...
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2answers
1k views

Implementing analog multiplexers in LTSpice and Cadence Virtuoso

Is there any model for Analog Multiplexer compatible with LTSpice or Cadence Virtuoso? A simple 2:1 multiplexer is implemented in LTSpice as a SPDT switch. So how to implement a 4:1, 8:1 or 16:1 ...
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1answer
68 views

Cadence Virtuoso - Cell Parameterized [closed]

Please see attached. I am unable to view the Poly, Metal, Cont layers for the PMOS & NMOS instances. Need a bit of assitance on how to fix this issue
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1answer
183 views

Allegro OrCAD Capture: Crashing after DRC check [closed]

Issue: The OrCAD Capture software by Cadence is continually crashing. The version I have is SPB_16.5. Problem: I can run ONE DRC check fine, however; when I run another DRC on my schematic, the ...
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1answer
165 views

Resettable counter using JK flip

I want to design a binary counter in Cadence that counts pulses in every consecutive 50 nano seconds but i want it to be reset at the end of each 50 ns and shortly - so that it doesn't miss any pulse -...
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3answers
247 views

Demodulation of a data

As seen in this picture, I have a circuit that has created those desired pulses in the output. There is a last stage in my circuit and that is: Translating the times that more pulses have happened to "...
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1answer
153 views

Difference between conventional Eye-diagram voltage plot and “Eye-density” plot in ADS Keysight Simulation

I know what is eye diagram. It is the sampled voltage plot at the clock frequency (Usually) of my circuit and superimposed. If the logic 0 corresponds ...
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0answers
148 views

How to setup and simulate differential TDR (Time Domain Reflectometry) in Cadence

I want to do differential TDR simulation in cadence virtuoso. I have a differential channel, made of Tlines and interconnects (passive componenets). How to setup the TDR simulation to get impedance ...
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1answer
33 views

Absolute value block in AHDL library

I'm using the absolute value block from AHDL library in cadence virtuoso. I need to take absolute value of a signal which varies from -5 to +5 volts. Since the voltage passes through 0 volts when ...
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1answer
59 views

transient noise plot in virtuoso

I was simulating a transient test on an SRAM cell, added a transient noise of 1-30MHZ frequency with 100 multiple simulations and calculated a VQ-QB graph(dots). I want to be able to only plot the ...
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1answer
82 views

Duplicate IDs in VCD files

I peered into one of the VCD files that was generated when I ran a Verilog testbench using Cadence's ncverilog suite. There, I noticed many wires (belonging to different module scopes though) that had ...
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1answer
965 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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2answers
228 views

How to correct voltage overshoot in clock divider output?

I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a ...
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1answer
452 views

Why use more than one contact in VLSI layout?

I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
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130 views

self-quenched oscillator

I am trying to simulate a circuit which is composed of an oscillator which oscillates and reaches a maximum oscillation amplitude, then there's a peak detector that is following the peak of ...
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2answers
250 views

How to create an OOK signal in ADS

I'm trying to make an OOK modulated signal in ADS. I need a random bit generator, and a block to multiply a sinusoidal signal with that random pulse. I did this in Cadence by the 'rand_bit_stream' and ...