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Designing a D-FF in Virtuoso to create 90 degrees phase shift

I am currently trying to design a digital circuit in Cadence to produce a 90 degrees phase shift to a CLK signal within my current circuit. Below is an image of a D-FF setup as well as the output ...
soccernismo's user avatar
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73 views

6T SRAM Simulation on Cadence

I had recently studied about SRAM in Computer Architecture and learned that a SRAM Cell is actually made up of MOSFETs. I was curious to learn more about the architecture of SRAM, for which I read ...
Inder Saini's user avatar
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15 views

Wireopt variable in cadence virtuoso ADE simulator window

I am wondering about a variable in my simulator & output window in cadence virtuoso. It is wireopt. It is there by default when I start any simulation in ADE/ADE XL window. And the value is this. ...
aguntuk's user avatar
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1 answer
64 views

Designing an oscillator circuit in Cadence Virtuoso, but not sure why the comparator portion is not working

I am currently in the process of designing and testing an oscillator design which consists of a current reference and a comparator based on common gate topology (right hand side circled in red.) The ...
soccernismo's user avatar
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Short Circuit Transconductance Cadence

Hello, I am curious about hand calculation about overall Gm by using short circuit transconductance. I got M2 of gm is 1.176mA/V, M2 of gmb is 0.2078mA/V. It should be around 1.14mA/V by using short ...
jsdklfsldn's user avatar
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1 answer
73 views

Output Resistance in Cadence

Hello, I am trying to find out output resistance of opamp. Is the way that put the small signal model source at the output, set the voltage at operating point 0.9028V, and set the AC amplitude for 5mV....
jsdklfsldn's user avatar
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63 views

Help needed in LDO design

I am trying to design a linear regulator. I started with a macro model for the error amplifier and added a pass stage. 50mA idc is the load. My desired output is 1.5V and Vin=1.8V. IBM180nm models. ...
desi_noob's user avatar
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1 answer
81 views

Two stage differential amplifier as comparator [closed]

I used two stage differential opamp as comparator but I'm getting the output -ve voltage range. I have to get high (1.8 V) when it is greater than reference voltage and low (0 V) when less than ...
had's user avatar
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2 answers
111 views

cascode NMOS (virtuoso)

I have run across a problem. When I was trying to design a cascode amplifier that was gain>=10V I have succeeded to make it. The rout in gm/Id method is 1.58M ohms. When I typed the width and ...
jsdklfsldn's user avatar
1 vote
1 answer
198 views

error in cadence virtuoso while simulation no matter what the circuit is

schematic of circuit: using gdpk90 , transient analysis with stop time 5m and accuracy moderate. error getting : Warning from spectre during initial setup. WARNING (CMI-2477): I0.PM0: ...
had's user avatar
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Subthreshold Operation for Beta Multiplier Circuit

I am currently in the process of designing a Beta Multiplier Circuit using 120 nm technology, and want to run the circuit in subthreshold operation with (Vgs < 4*Vthermal). Below are some captures ...
soccernismo's user avatar
2 votes
1 answer
129 views

Is this the leakage current of a MOSFET?

I'm trying to understand the leakage current characteristics of a 130nm PDK in Cadence. I set up a testbench by grounding the gate and source terminals of a nmos FET, and setting the drain voltage to ...
Jack Black's user avatar
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1 answer
213 views

Conversion from Allegro *.brd to *.alg

Can anyone who works with Cadence Allegro convert a *.brd file to *.alg ?
Douglas Lima's user avatar
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31 views

Export Cadence Virtuoso Schematic to tikz

To export the layout to tikz, there's this great tool available: https://github.com/electronics-and-drives/ml2tikz I thought there was a similar tool to export the schematic to tikz but I can't find ...
Holzbaum's user avatar
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83 views

PSRR of a folded-cascode op amp varies a lot in corners

My design of fc op amp can't pass Monte Carlo (mc) analysis in Cadence Virtuoso because my PSRR varies significantly in corners. PSRR varies from 80dB to 120dB in corners, where temperature changes ...
narutouzumaki 99's user avatar
1 vote
1 answer
84 views

Verilog output register not changing

I have to use combinational logic to write Verilog for a circuit schematic. However, my output registers, CLK1 and CLK2, do not change and are stuck at the initial values. What is causing this bug? ...
Gabriel Zhang's user avatar
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53 views

Fiber weave effect calculation for a PCB

How can I calculate the angle offset and maximum length? Here is my stack-up: You can consider my signal to be routed in layer 3. Please help in understanding the calculation and concept of it.
Ram_R's user avatar
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608 views

Simulating cmos comparator on cadence virtuoso

I am trying to simulate the following cmos comparator circuit using cadence virtuoso spectre. Here's my schematic on cadence: I am using the following test bench to simulate the circuit with Ibias = ...
ah286's user avatar
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1 vote
2 answers
279 views

Why doesn't this amplifier work?

I'm trying to understand how this circuit (a low-noise amplifier) works from this paper. According to my understanding, the first stage is a class AB amplifier and the second stage is a simple ...
Jack Black's user avatar
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1 answer
73 views

How to explain this low-pass phenomenon?

I'm trying to understand how a coupling capacitor works, and build the following circuit. The transfer function (obtained from an AC simulation) from the voltage source (V2) to the gate voltage of the ...
Jack Black's user avatar
2 votes
0 answers
226 views

How to extract parasitic capacitance caused by PCB layout? [closed]

I'm working on a precision DC measurement PCB design based on the capacitance-integration method. The key element integration capacitor is quite precise. However, due to my specific PCB layout design, ...
Robert Liang's user avatar
2 votes
0 answers
204 views

Cadence Virtuoso CMOS layout: MIMcap become unrecognised after instantiating a new component

I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBLs. ...
Nitrogen's user avatar
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0 answers
574 views

Cadence genus synthesis script issue

I have written a genus synthesis script for synthesizing my design of Direct Digital Synthesis for a University project. The DDS design is working properly in simulation and is fully synthesizable. I ...
blackblade's user avatar
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0 answers
503 views

5T OTA Vout in Cadence simulation is always just VDD?

I'm working on an 5T OTA with the following schematic: Here's the simulation circuit: I'm using a VDD = 2.5V since the transistors are rated for that in the model library I'm using. My issue is that ...
MFerguson's user avatar
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1 answer
123 views

How to know all possible hierarchies in Cadence Innovus for a given design?

I want to know all the possible hierarchies in the design like dl1, dl1/dl2, dl1/dl2/dl3, etc. where dl1, dl2, and dl3 indicate the depths in the design. Is there any command for this?
Nagendra Prasad's user avatar
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0 answers
113 views

The following branches form a loop of rigid branches (shorts) when added to the circuit in Cadence Virtuoso

I'm trying to build a Full Adder in Cadence Virtuoso using 2inp NAND Gate symbol. But I'm getting the following error, This is the circuit, Schematic of the symbol, What is the mistake and the ...
Dominic Immanuel's user avatar
1 vote
0 answers
80 views

How to measure noise in cadence with this RF circuit?

This is the circuit where i want to measure the noise. I'm new in cadence so i dont know how to do it. I tried making putting some things here but it doesn't work.
Scipio's user avatar
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1 answer
123 views

Trying to implement a low-pass filter with a LNA as an op-amp

I'm trying to implement a low-pass filter using this circuit configuration: I first tried implementing in Cadence using an ideal op-amp: At 1 MHz I already have around -2.29 dB, so it's working as ...
Scipio's user avatar
  • 793
1 vote
1 answer
661 views

What is the meaning of a negative capacitance? - Cadence Virtuoso

What is the meaning of a negative capacitance in cadence virtuoso? Here in the following image, I just want to find the capacitance of transistors using "print-->DC operating point". Can ...
mohammad rezza's user avatar
1 vote
1 answer
199 views

What is the meaning of "a" and "z" in capacitor value - Cadence Virtuoso

What is the meaning of "a" and "z" in capacitor value? Here is the image: I think "a" is angstrom, But I am not sure about it.
mohammad rezza's user avatar
1 vote
0 answers
42 views

How can I find critical field in tsmc65 transistor parameter?

How can I find critical field in tsmc65 transistor parameters? Critical field is the field which electron velocity in transistor go into the saturation region.
mohammad rezza's user avatar
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1 answer
450 views

How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso?

How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso? They are all abbreviated and there is not any guide there. For example, I want to know the value of "...
mohammad rezza's user avatar
1 vote
0 answers
1k views

How to find (mobility*Cox) and Vth

How to find "mobility*Cox" and "threshold voltage" of NMOS in cadence virtuoso? I have performed DC analysis in schematic environment and using NMOS model parameters, I tried to ...
mohammad rezza's user avatar
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1 answer
347 views

What is the meaning of "Unit Size NMOS (W=5*325nm/L=5*65nm)"

What is the meaning of the following sentence: Simulate a Unit Size NMOS (W=5 * 325nm/L=5 * 65nm) and PMOS (W=5325nm/L=565nm) with in CMOS technology. Well, this transistor is a MOSFET with 65nm ...
mohammad rezza's user avatar
-1 votes
1 answer
60 views

In Cadence AWR, why do the theoretical values for components yield much lower results than the optimized values?

I used Cadence AWR Design Environment to simulate a bandpass filter from 1.6 GHz to 3.2 Ghz, in both Pi and T formats. I calculated the theoretical values for each component and put them in the ...
Kuchi Yashwanth's user avatar
1 vote
1 answer
1k views

Cadence Allegro/PCB Editor: Change mechanical pin to electrical pin

Inside a package/footprint I accidentally deleted the texts of the pin numbers. Thus the electrical pins became mechanical pins. Can I somehow reverse this process and change the mechanical pins back ...
Charly's user avatar
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1 answer
94 views

How to measure the retention time of a capacitor?

I am trying to build a very simplisitic DRAM in cadence using MOM/MIM capacitors. I am using models from the CMOS and FD-SOI processes and I'd like to measure the retention time I can expect from ...
Leonhard Euler's user avatar
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0 answers
143 views

Erroneous oscillation voltage for LC Tank in Cadence Virtuoso

I simulated an LC tank with an ideal inductor and capacitor. The inductor's initial condition was 0 and the capacitor's was 300 mV. I expected it to oscillate with an amplitude of 300 mV, but it ...
SAYAN KUMAR's user avatar
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0 answers
487 views

Cadence Virtuoso Schematic: Input pin goes to 2 different nets

I have a silly problem regarding input pins connecting to 2 different nets of a circuit in cadence virtuoso. Due to non-sharable agreement, I cannot share the actual circuit. But I can provide simple ...
aguntuk's user avatar
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1 vote
1 answer
136 views

Allowed amount of input wreal data type at verilog-ams

I'm a newbie at using Verilog-ams and also I want to write a module for flash ADC for a specific application. I need to confine my voltages reference so I wrote this Verilog-ams code for testing input ...
Marziye Hasanshahi's user avatar
0 votes
1 answer
288 views

"Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
Souhardya Mondal's user avatar
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0 answers
93 views

Use half of an MUX

Can someone give me the schematics of this half 74153 mux?
antisocialkid's user avatar
1 vote
2 answers
181 views

How can I match the impedance in the distributed transmission line model?

I'm trying to do impedance matching for an inverter transmitting signal through a transmission line in Cadence. The transmission line is modelled as a number of RLC elements(\$R_{TL}=0.1\Omega\$,\$L_{...
Jack Black's user avatar
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0 answers
50 views

Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit

I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS ...
aguntuk's user avatar
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0 votes
1 answer
263 views

Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic

I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both P-MOS and N-MOS.) I know I can increase the length directly. As connecting MOSFETs in series increases length, can I somehow ...
aguntuk's user avatar
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2 votes
1 answer
1k views

Tips on how to increase the gain and lower the noise factor of a LNA

Hey guys I am designing a LNA biases by a 3.3 V source and tuned to 2.5 GHz. Here is the schematics, the testbench and some results (s parameters analysis). I would like to know if there is a way of ...
Granger Obliviate's user avatar
0 votes
1 answer
269 views

Output Voltage Range of Op amps

I'm building a TIA circuit in Cadence as shown below. OP_LN is a module from AMS 0.35um Technology (datasheet). I think the configuration is correct. And I'm expecting \$V_{\text{out}}\$ would be ...
Jack Black's user avatar
1 vote
0 answers
250 views

How to add NCSU FreePDK45 to Cadence Virtuoso Library?

I'm looking for a comprehensive guide on how to add FreePDK45 to Cadence Virtuoso Library (2015 version). The installation guides included are not clear for first timers, and other resources available ...
eln05's user avatar
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1 vote
1 answer
114 views

Feedback in Power Amplifier

I am working on the design of a RF power amplifier. I want to use a feedback from the drain to gate. How can I determine the type of feedback (positive,negative) used. I am using a series RC feedback ?...
Yash 's user avatar
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1 vote
0 answers
179 views

How can I find the errors on my layout?

I am losing my mind not being able to find the error on my layout. I feel like I am looking for a nail in the mud. I am getting the DRC error : MET1 pin outside met1 But I look and look and LOOK and ...
Granger Obliviate's user avatar