Questions tagged [cadence]

For anything related to Cadence: EDA Tools and IP for System Design Enablement

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1answer
107 views

Phase margin is 90 degrees but transient step response shows overshoot

The bode plot of the loop is as shown here The transient step response looks like this The block diagram looks something like this - Basically a single stage opamp(OPAMP in fig) with high gain(...
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1answer
22 views

What does the layer structures and the macro structre describe in a LEF file?

I want to know what is the exact format of a LEF file. For example, I have the following format of LEF file ... I want to know what the layer and macro structures describe. Also, how many layer and ...
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2answers
147 views

What tool produces this type of layout?

I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442 Alternate link for the ...
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1answer
45 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
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42 views

How do I fix an error message “expecting an expression or operand” when reading an input file in cadence vhdl?

How do I fix the following error message? ...
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1answer
38 views

Plotting G(t) of an oscillator in Cadence

I have a cross-coupled NMOS-only oscillator that has its bias voltage changing so its transconductance is also changing over time. I want to plot its transconductance (G(t)=G0-gm/2) over time in ...
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37 views

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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1answer
45 views

Peaks in XOR-XNOR Waveforms

I have been designing some two input XOR-XNOR circuits using Cadence Virtuoso. All of them are working as expected but there is a little problem when both the inputs make a transition; the XOR and ...
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1answer
19 views

common source pole calculation vs. simulation

I would like to compare my pole simulation results to my hand calculations, I'm receiving quite a big error. when simulating a Common Source stage without output capacitance load there is a big ...
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1answer
146 views

Dynamic phase Routing In Allegro

My doubt is regarding the dynamic phase control while routing differential pairs in allegro. If anyone knows kindly clear my doubts on these questions. For your reference, I have attached a snapshot ...
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0answers
43 views

Anneal Placement

I'm doing a practice assignment, and I cant seem to understand this question. They give 6 gates in a small 6x6 grid. Each gate is drawn as a circle with number. There are 4 nets, labeled A, B, C and ...
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1answer
55 views

Latch-based sense amplifier design using CADENCE Virtuoso 65 nm technology

I am trying to design a latch-based sense amplifier to sense about 55mV voltage difference using 65nm technolgy, it takes differential input, and should get from it differential output too where it ...
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42 views

How to simulate under skewed process corners (SF, FS, SFA, FSA) in Cadence 65nm?

I'm testing a circuit under different process corners and I already know how to simulate under FF, SS and TT process corners. However, I'm getting inconsistent results in the skewed corners (SF, FS, ...
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55 views

Liberate - Custom Cell Characterization

Tools and Tech: ST 65nm | LIBERATE Library Characterization Platform (x86_64) 12.1.4 (altos 121) | Cadence Virtuoso 6.1.5-64b | Calibre Interactive - PEX v2012.4_16.11 I am trying to characterize a ...
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21 views

Drain capacitance of CMOS inverter

How to find the total drain( NMOS+PMOS) capacitance of CMOS inverter in cadence virtuoso?
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67 views

Ferroelectric Capacitor model using verilog-a

I am trying to develop a behavioral model of a ferroelectric capacitor using verilog-a. The ferroelectric material is HfO2 in between the capacitor plates. I know the polarization hysteresis formula ...
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1answer
166 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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56 views

transient output file option in pspise

I want to save my simulation result in capture every 100us and export them in text file. I went to simulation settings>Analysis>output file option and changed print values in output file every 100us (...
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176 views

Simulate H Bridge in Pspice

I want to simulate an H-bridge in pspice but it doesn't work and Z3 and Z6 (High side and low side IGBTs) can not drive at the same time. Here is my schematic
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1answer
42 views

How to Reconfigure a Current Sense Amplifier Pspice Model

I downloaded the .lib Spice library for the MAX4172 and imported it into OrCad, available from: https://www.maximintegrated.com/en/products/analog/amplifiers/MAX4172.html/tb_tab2 The library file ...
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2answers
134 views

Does the capacitance values matter in a full wave voltage doubler?

I've simulated the following schematic on Cadence, and another less professional simulator called 'everycircuit'. I initially had a C1 = C2 = 10uF which simulated correctly on both simulators. Then I ...
1
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1answer
66 views

PSPICE graphs work separately for subcircuits, wrong when combined?

I'm working on a pulse generation circuit that will be used to drive an ultrasonic transducer. The following circuit is giving an unexpected output. It might look complicated, but really it can be ...
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2answers
81 views

Is Cadence unable to simulate AC to DC converters using simple full bridge rectifier?

I've tried several different topologies, such as the full bridge rectifier and the following which I've successfully tested on other simulators. However, on Cadence I always end up getting static ...
1
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1answer
40 views

Why does AC/Sweep in Cadence always require a starting and stopping frequency?

It seems as if there is no way to simply test a circuit with an AC voltage source at a single frequency. How does someone test a circuit that plugs into the main voltage at 60Hz? Is it really ...
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1answer
85 views

Using PSPICE model of gate-driver from manufacturer

I have found a PSPICE model for a part I'm interested in. ISL55110 Datasheet: https://www.mouser.com/datasheet/2/698/isl55110-11-1302115.pdf Manufacturer PSPICE Model: https://www.renesas.com/cn/zh/...
1
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1answer
104 views

PSPICE simulation of capacitor voltage and current disagrees with math

I'm testing a simple enough circuit on PSPICE. The zener has a BV = 220V, so the capacitor has a voltage of 220V until the switch closes. Using the time equation for voltage of a capacitor: Vc(t) = ...
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2answers
679 views

Implementing analog multiplexers in LTSpice and Cadence Virtuoso

Is there any model for Analog Multiplexer compatible with LTSpice or Cadence Virtuoso? A simple 2:1 multiplexer is implemented in LTSpice as a SPDT switch. So how to implement a 4:1, 8:1 or 16:1 ...
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1answer
48 views

Cadence Virtuoso - Cell Parameterized [closed]

Please see attached. I am unable to view the Poly, Metal, Cont layers for the PMOS & NMOS instances. Need a bit of assitance on how to fix this issue
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1answer
133 views

Allegro OrCAD Capture: Crashing after DRC check [closed]

Issue: The OrCAD Capture software by Cadence is continually crashing. The version I have is SPB_16.5. Problem: I can run ONE DRC check fine, however; when I run another DRC on my schematic, the ...
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1answer
134 views

Resettable counter using JK flip

I want to design a binary counter in Cadence that counts pulses in every consecutive 50 nano seconds but i want it to be reset at the end of each 50 ns and shortly - so that it doesn't miss any pulse -...
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3answers
203 views

Demodulation of a data

As seen in this picture, I have a circuit that has created those desired pulses in the output. There is a last stage in my circuit and that is: Translating the times that more pulses have happened to "...
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1answer
116 views

Difference between conventional Eye-diagram voltage plot and “Eye-density” plot in ADS Keysight Simulation

I know what is eye diagram. It is the sampled voltage plot at the clock frequency (Usually) of my circuit and superimposed. If the logic 0 corresponds ...
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0answers
113 views

How to setup and simulate differential TDR (Time Domain Reflectometry) in Cadence

I want to do differential TDR simulation in cadence virtuoso. I have a differential channel, made of Tlines and interconnects (passive componenets). How to setup the TDR simulation to get impedance ...
0
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1answer
31 views

Absolute value block in AHDL library

I'm using the absolute value block from AHDL library in cadence virtuoso. I need to take absolute value of a signal which varies from -5 to +5 volts. Since the voltage passes through 0 volts when ...
0
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1answer
54 views

transient noise plot in virtuoso

I was simulating a transient test on an SRAM cell, added a transient noise of 1-30MHZ frequency with 100 multiple simulations and calculated a VQ-QB graph(dots). I want to be able to only plot the ...
0
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1answer
72 views

Duplicate IDs in VCD files

I peered into one of the VCD files that was generated when I ran a Verilog testbench using Cadence's ncverilog suite. There, I noticed many wires (belonging to different module scopes though) that had ...
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1answer
564 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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2answers
192 views

How to correct voltage overshoot in clock divider output?

I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a ...
1
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1answer
354 views

Why use more than one contact in VLSI layout?

I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
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0answers
115 views

self-quenched oscillator

I am trying to simulate a circuit which is composed of an oscillator which oscillates and reaches a maximum oscillation amplitude, then there's a peak detector that is following the peak of ...
0
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2answers
217 views

How to create an OOK signal in ADS

I'm trying to make an OOK modulated signal in ADS. I need a random bit generator, and a block to multiply a sinusoidal signal with that random pulse. I did this in Cadence by the 'rand_bit_stream' and ...
0
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1answer
52 views

regions in cadence

I have a circuit that in it mosfets go through different regions (the circuits's core is an oscillator, I quench my oscillator by some mechanism and then let it oscillate again till the amplitude of ...
1
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2answers
218 views

What is this section category in Model Library Setup in Cadence Virtuoso ADE L?

I usually leave it at default while constructing circuit in Cadence Virtuoso. I didn't really understand what it is or why it is used for.
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1answer
51 views

Problem making an OOK current signal using pvcvs

I am trying to make an OOK current signal using pvcvs in cadence (I tried pcccs but i couldn't find out what the settings were and it didn't work), and in order to change the output to current i used ...
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2answers
2k views

Where is the pspice “output file”?

This is the error message when trying to run a simulation for one of my models ...
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2answers
222 views

what is the ideal number of contacts to be placed in NMOS and PMOS when drawing layout in Cadence virtuoso

I am trying to draw a layout for inverter and i am not sure about how many contacts to be placed in the diffussion region of NMOS and PMOS and what is the reason behind selecting that particular ...
0
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1answer
605 views

Cadence: use voltage as a parameter to change resistance

I designed a circuit that takes two user inputs ("vl" and "vh") and set a resistor value ((vh-vl)*100kOhm) that sets the gain of a inverting opamp amplifier. I am using Cadence and both vl and vh are ...
0
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2answers
183 views

Modulated input in cadence

I am giving a 25MHz signal input to pll for simulation in cadence. But I also want to modulate its frequencies from 1Khz to 2Mhz. But how to do the frequency modulation of a signal in cadence?
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1answer
829 views

Output Resistance of a High-Swing Cascode Current Mirror

I am wondering how to calculate the output resistance of a High-Swing Cascode Current Mirror from small-signal parameters, see question High-Swing Cascode Current Mirror for the circuit. First I ...
2
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1answer
205 views

LNA design question - series drain inductor

I am designing an LNA in Cadence that follows the schematic below very closely. This is taken directly from TH Lee's book on RF integrated circuit design. The book says that \$L_d\$ and \$C_L\$ ...