Questions tagged [cadence]
For anything related to Cadence: EDA Tools and IP for System Design Enablement
181
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2
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64
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How to extract parasitic capacitance caused by PCB layout? [closed]
I'm working on a precision DC measurement PCB design based on the capacitance-integration method. The key element integration capacitor is quite precise. However, due to my specific PCB layout design, ...
- 41
2
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0
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58
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Cadence Virtuoso CMOS layout: MIMcap become unrecognised after instantiating a new component
I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBLs. ...
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0
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0
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176
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Cadence genus synthesis script issue
I have written a genus synthesis script for synthesizing my design of Direct Digital Synthesis for a University project. The DDS design is working properly in simulation and is fully synthesizable. I ...
- 378
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0
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117
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5T OTA Vout in Cadence simulation is always just VDD?
I'm working on an 5T OTA with the following schematic:
Here's the simulation circuit:
I'm using a VDD = 2.5V since the transistors are rated for that in the model library I'm using.
My issue is that ...
- 207
0
votes
1
answer
61
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How to know all possible hierarchies in Cadence Innovus for a given design?
I want to know all the possible hierarchies in the design like dl1, dl1/dl2, dl1/dl2/dl3, etc. where dl1, dl2, and dl3 indicate the depths in the design. Is there any command for this?
- 111
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95
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Verilog A modelling of THz detector
I am working on modelling a THz detector in Verilog A. Graphene FET can be used as a THz detector which generates DC voltage proportional to the intensity of the input THz signal as given by the ...
- 74
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56
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The following branches form a loop of rigid branches (shorts) when added to the circuit in Cadence Virtuoso
I'm trying to build a Full Adder in Cadence Virtuoso using 2inp NAND Gate symbol. But I'm getting the following error,
This is the circuit,
Schematic of the symbol,
What is the mistake and the ...
1
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0
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49
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How to measure noise in cadence with this RF circuit?
This is the circuit where i want to measure the noise.
I'm new in cadence so i dont know how to do it. I tried making putting some things here but it doesn't work.
- 773
0
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1
answer
79
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Trying to implement a low-pass filter with a LNA as an op-amp
I'm trying to implement a low-pass filter using this circuit configuration:
I first tried implementing in Cadence using an ideal op-amp:
At 1 MHz I already have around -2.29 dB, so it's working as ...
- 773
1
vote
1
answer
336
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What is the meaning of a negative capacitance? - Cadence Virtuoso
What is the meaning of a negative capacitance in cadence virtuoso?
Here in the following image, I just want to find the capacitance of transistors using "print-->DC operating point". Can ...
- 442
1
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1
answer
117
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What is the meaning of "a" and "z" in capacitor value - Cadence Virtuoso
What is the meaning of "a" and "z" in capacitor value? Here is the image:
I think "a" is angstrom, But I am not sure about it.
- 442
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0
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284
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Cadence Virtuoso error: Expression evaluation failed
How can I solve this error in Cadence Virtuoso calculator?
expression evaluation failed: waveVsWave(?x IDC("/V1/PLUS") ?y OP("/M0","ron"))
I just want to show the ...
- 442
1
vote
0
answers
35
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How can I find critical field in tsmc65 transistor parameter?
How can I find critical field in tsmc65 transistor parameters? Critical field is the field which electron velocity in transistor go into the saturation region.
- 442
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140
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How can I plot "Vdsat" VS "Vgs" in Cadence Virtuoso?
How can I plot "Vdsat" VS "Vgs" in Cadence Virtuoso? I can place a voltage supply at the Vgs (gate-source voltage), then I give to its value a variable.
After that, I can define ...
- 442
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1
answer
168
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How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso?
How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso? They are all abbreviated and there is not any guide there.
For example, I want to know the value of "...
- 442
1
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0
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391
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How to find (mobility*Cox) and Vth
How to find "mobility*Cox" and "threshold voltage" of NMOS in cadence virtuoso?
I have performed DC analysis in schematic environment and using NMOS model parameters, I tried to ...
- 442
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1
answer
145
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What is the meaning of "Unit Size NMOS (W=5*325nm/L=5*65nm)"
What is the meaning of the following sentence:
Simulate a Unit Size NMOS (W=5 * 325nm/L=5 * 65nm) and PMOS
(W=5325nm/L=565nm) with in CMOS technology.
Well, this transistor is a MOSFET with 65nm ...
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-1
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1
answer
36
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In Cadence AWR, why do the theoretical values for components yield much lower results than the optimized values?
I used Cadence AWR Design Environment to simulate a bandpass filter from 1.6 GHz to 3.2 Ghz, in both Pi and T formats.
I calculated the theoretical values for each component and put them in the ...
1
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1
answer
598
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Cadence Allegro/PCB Editor: Change mechanical pin to electrical pin
Inside a package/footprint I accidentally deleted the texts of the pin numbers. Thus the electrical pins became mechanical pins. Can I somehow reverse this process and change the mechanical pins back ...
- 659
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1
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72
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How to measure the retention time of a capacitor?
I am trying to build a very simplisitic DRAM in cadence using MOM/MIM capacitors. I am using models from the CMOS and FD-SOI processes and I'd like to measure the retention time I can expect from ...
- 396
0
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0
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87
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Erroneous oscillation voltage for LC Tank in Cadence Virtuoso
I simulated an LC tank with an ideal inductor and capacitor. The inductor's initial condition was 0 and the capacitor's was 300 mV.
I expected it to oscillate with an amplitude of 300 mV, but it ...
0
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0
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245
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Cadence Virtuoso Schematic: Input pin goes to 2 different nets
I have a silly problem regarding input pins connecting to 2 different nets of a circuit in cadence virtuoso. Due to non-sharable agreement, I cannot share the actual circuit. But I can provide simple ...
- 13
1
vote
1
answer
90
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Allowed amount of input wreal data type at verilog-ams
I'm a newbie at using Verilog-ams and also I want to write a module for flash ADC for a specific application.
I need to confine my voltages reference so I wrote this Verilog-ams code for testing input ...
0
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1
answer
186
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"Tiny " XOR gate simulation not working
I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply.
Here is the schematic in Cadence. Doing a
DC simulation, I am not getting proper voltages at ...
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0
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65
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0
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0
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43
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What is the minima rule for a Metal 1 layer for the 2 contacts on a poly shown on the figure? I'm using 0.18um library
Contact on a poly using 0.06 spacing for the metal 1 layer
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1
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2
answers
132
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How can I match the impedance in the distributed transmission line model?
I'm trying to do impedance matching for an inverter transmitting signal through a transmission line in Cadence. The transmission line is modelled as a number of RLC elements(\$R_{TL}=0.1\Omega\$,\$L_{...
- 177
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0
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39
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Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit
I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS ...
- 13
0
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1
answer
197
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Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic
I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both P-MOS and N-MOS.)
I know I can increase the length directly. As connecting MOSFETs in series increases length, can I somehow ...
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2
votes
1
answer
709
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Tips on how to increase the gain and lower the noise factor of a LNA
Hey guys I am designing a LNA biases by a 3.3 V source and tuned to 2.5 GHz.
Here is the schematics, the testbench and some results (s parameters analysis). I would like to know if there is a way of ...
- 1,391
0
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1
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173
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Output Voltage Range of Op amps
I'm building a TIA circuit in Cadence as shown below. OP_LN is a module from AMS 0.35um Technology (datasheet). I think the configuration is correct.
And I'm expecting \$V_{\text{out}}\$ would be ...
- 177
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0
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180
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How to add NCSU FreePDK45 to Cadence Virtuoso Library?
I'm looking for a comprehensive guide on how to add FreePDK45 to Cadence Virtuoso Library (2015 version). The installation guides included are not clear for first timers, and other resources available ...
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vote
1
answer
104
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Feedback in Power Amplifier
I am working on the design of a RF power amplifier. I want to use a feedback from the drain to gate. How can I determine the type of feedback (positive,negative) used. I am using a series RC feedback ?...
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0
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127
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How can I find the errors on my layout?
I am losing my mind not being able to find the error on my layout. I feel like I am looking for a nail in the mud.
I am getting the DRC error
: MET1 pin outside met1
But I look and look and LOOK and ...
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0
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1
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351
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What is this error on DRC Cadence layout
I'm doing the layout of an amplifier on Cadence. I've run the DRC error checker and I don't understand what message is this, can someone help me?
- 1,391
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1
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148
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Windowing FFT: spectral leakage vs ENOB
I am using Cadence to perform full speed testing of a 4-bit SAR ADC using the FFT and non-coherent sampling.
I've obtained the ENOB and the spectra of the output signal using first the rectangular ...
- 1,391
1
vote
1
answer
469
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Op Amp design - open loop gain 73dB, closed loop gain -200dB
This is my first time designing an op amp, using 180nm in Cadence. Two stage design, 1st stage is NMOS differential pair with PMOS current mirror load, second stage is PMOS CS with Miller capacitor. ...
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1
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235
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Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)
I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well.
For ...
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1
answer
474
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Is it possible to import CAD model files into LTspice?
There are very beneficial and comprehensive collections of CAD models provided by Mouser or other websites. Is it possible to use them in LTspice?
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vote
1
answer
163
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Difference between different solder mask classes
I use Cadence Allegro 16.6V for PCB designing. We have option to use solder mask sub class from different classes like "Board geometry" and "package geometry".
I know that "...
- 197
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0
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230
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How to set a minimum distance between components in OrCAD PCB Designer?
I am using OrCAD PCB Designer Professional 17.4 and I can't setup the minimum distance between components. This is the "DFA Constraints Dialog" from Allegro in which you can make the setup, ...
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1
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374
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Determination of beta effective and threshold voltage of N-33 MOSFET from UMC_180nm library
I have DC simulated the N-33 MOSFET from the UMC_180nm library in Cadence and have found different values of beta effective for different values of Vgs as attached below.
The calculated beta effective ...
2
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0
answers
521
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How do I simulate an RF mixer in PSS or harmomic balance with an autonomous local oscillator?
I am designing a CMOS RF downconversion signal chain comprised of a local oscillator and mixer (the LNA is not yet included) using the Cadence Virtuoso Circuit Design Suite with ADE XL as my simulator....
- 18.1k
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1
answer
134
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How can I add reference return path via (ground via) in a symmetric way in PCB Editor?
I would like to add symmetric via (return path via in the middle) using PCB Editor as shown below.
I can add via manually. I just wanted to make sure it is symmetric to the two diff-pair fanouts as ...
- 319
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1
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82
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Why do linear time varying system exhibit frequency conversion
I am trying to understand the theory behind spectreRF simulations. Specifically, PSS (periodic steady state) and PAC (periodic AC)
The following concept keeps getting mentioned
"After a PSS ...
- 117
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0
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2k
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How to use the dft function in Cadence Virtuoso Calculator?
I had the following setting for the dft function in Cadence Virtuoso Calculator:
But it gave me some negative values in the spectrum:
So why there are negative values? Is there anything wrong in the ...
- 377
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2
answers
466
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How can I draw layout for 2 NMOS having different body potential?
I am trying to understand how I can draw the layout of the following circuit where the 2 NMOSs have different body potential. Any suggestion will be highly appreciated.
Thanks!
- 109
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1
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38
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Understanding two Multivibrator models
I simulated the two multivibrator models in CMOS technology using the cadence tool. I was expecting the model 2 with Schmitt trigger(ST) will show robustness in PVT (Process Voltage temperature) ...
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0
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168
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Confusion regarding connecting nport in cadence while trying to find input impedance
I am a little bit confused on how to to connect the nport in the case where I try to find looking in impedance of a transmission line which is loaded by a 1pF capacitor on the one side.
As shown in ...
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119
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What is the equation for "beff", i.e., "Gain Factor in Saturation" in BSIM4?
Using the device parameter list in Cadence, I found out that ID follows this equation exactly:
ID = 1/2 * beff * vgt**2
I also found out that ...
- 305