Questions tagged [cadence]

For anything related to Cadence: EDA Tools and IP for System Design Enablement

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Use half of an MUX

Can someone give me the schematics of this half 74153 mux?
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What is the minima rule for a Metal 1 layer for the 2 contacts on a poly shown on the figure? I'm using 0.18um library

Contact on a poly using 0.06 spacing for the metal 1 layer
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How can I match the impedance in the distributed transmission line model?

I'm trying to do impedance matching for an inverter transmitting signal through a transmission line in Cadence. The transmission line is modelled as a number of RLC elements(\$R_{TL}=0.1\Omega\$,\$L_{...
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Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit

I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS ...
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Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic

I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both P-MOS and N-MOS.) I know I can increase the length directly. As connecting MOSFETs in series increases length, can I somehow ...
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Tips on how to increase the gain and lower the noise factor of a LNA

Hey guys I am designing a LNA biases by a 3.3 V source and tuned to 2.5 GHz. Here is the schematics, the testbench and some results (s parameters analysis). I would like to know if there is a way of ...
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Output Voltage Range of Op amps

I'm building a TIA circuit in Cadence as shown below. OP_LN is a module from AMS 0.35um Technology (datasheet). I think the configuration is correct. And I'm expecting \$V_{\text{out}}\$ would be ...
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How to add NCSU FreePDK45 to Cadence Virtuoso Library?

I'm looking for a comprehensive guide on how to add FreePDK45 to Cadence Virtuoso Library (2015 version). The installation guides included are not clear for first timers, and other resources available ...
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Keeping shapes/ polygons from going over same net trace in Cadence OrCAD?

I have an interesting situation where I have a current sense line that needs to be differential to ground. I'm trying to add copper pours to the top and bottom layers, however I can't pour over these ...
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Keysight ADS User-Defined Models to AWR/Virtuoso

everyone! In ADS Keysight it is possible to create a model - the so-called User-Defined Model. This is C++ code that describes the Y-matrix of the component. Is there the same possibility in AWR ...
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Feedback in Power Amplifier

I am working on the design of a RF power amplifier. I want to use a feedback from the drain to gate. How can I determine the type of feedback (positive,negative) used. I am using a series RC feedback ?...
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How can I find the errors on my layout?

I am losing my mind not being able to find the error on my layout. I feel like I am looking for a nail in the mud. I am getting the DRC error : MET1 pin outside met1 But I look and look and LOOK and ...
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What is this error on DRC Cadence layout

I'm doing the layout of an amplifier on Cadence. I've run the DRC error checker and I don't understand what message is this, can someone help me?
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Windowing FFT: spectral leakage vs ENOB

I am using Cadence to perform full speed testing of a 4-bit SAR ADC using the FFT and non-coherent sampling. I've obtained the ENOB and the spectra of the output signal using first the rectangular ...
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1 answer
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Op Amp design - open loop gain 73dB, closed loop gain -200dB

This is my first time designing an op amp, using 180nm in Cadence. Two stage design, 1st stage is NMOS differential pair with PMOS current mirror load, second stage is PMOS CS with Miller capacitor. ...
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Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)

I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well. For ...
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How to generate not-rounded text in AWR layout design?

In AWR software, I usually use Arial black font for my texts in my layout design. However, it is not a good font compared to fonts within other softwares. Does anyone know any font in AWR that has not ...
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Is it possible to import CAD model files into LTspice?

There are very beneficial and comprehensive collections of CAD models provided by Mouser or other websites. Is it possible to use them in LTspice?
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How to display the value of a parameter in a Verilog-A script using Cadence Virtuoso?

I ran a Verilog-A script in Cadence Virtuoso. I used the function $display() to print the value of some of the parameters in the script. However, I cannot find the values displayed on the CIW window. ...
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Difference between different solder mask classes

I use Cadence Allegro 16.6V for PCB designing. We have option to use solder mask sub class from different classes like "Board geometry" and "package geometry". I know that "...
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Spectre : Invalid component name was given as value of parameter

For https://github.com/promach/AC_analysis_methods/tree/main/GNT , why spectre throws me the following error ?
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How to set a minimum distance between components in OrCAD PCB Designer?

I am using OrCAD PCB Designer Professional 17.4 and I can't setup the minimum distance between components. This is the "DFA Constraints Dialog" from Allegro in which you can make the setup, ...
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Determination of Beta effective and Threshold Voltage of N-33 Mosfet of UMC_180nm library

I have DC simulated the N-33 Mosfet of UMC_180nm library in Cadence and have found different values of Beta effective for different values of Vgs as attached below. Also, the calculated Beta effective ...
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Do we need to define the delay, power and constraint templates for characterising a library (.lib) file out of post-layout netlists (transistor level)

I am designing standard cells at the transistor level and I want the characterize these cells into a library file (.lib). Do I need to define the delay, power and constraint templates (sequential) ...
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High impedance in current source for Iout=0

I'm simulating an APS pixel using a DC current source as input of the light source. The problem: a DC current source delivers power even when there is a high impedance state between its nodes. I have ...
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How do I simulate an RF mixer in PSS or harmomic balance with an autonomous local oscillator?

I am designing a CMOS RF downconversion signal chain comprised of a local oscillator and mixer (the LNA is not yet included) using the Cadence Virtuoso Circuit Design Suite with ADE XL as my simulator....
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How can I add reference return path via (ground via) in a symmetric way in PCB Editor?

I would like to add symmetric via (return path via in the middle) using PCB Editor as shown below. I can add via manually. I just wanted to make sure it is symmetric to the two diff-pair fanouts as ...
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Why do linear time varying system exhibit frequency conversion

I am trying to understand the theory behind spectreRF simulations. Specifically, PSS (periodic steady state) and PAC (periodic AC) The following concept keeps getting mentioned "After a PSS ...
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How to use the dft function in Cadence Virtuoso Calculator?

I had the following setting for the dft function in Cadence Virtuoso Calculator: But it gave me some negative values in the spectrum: So why there are negative values? Is there anything wrong in the ...
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135 views

How can I draw layout for 2 NMOS having different body potential?

I am trying to understand how I can draw the layout of the following circuit where the 2 NMOSs have different body potential. Any suggestion will be highly appreciated. Thanks!
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Understanding two Multivibrator models

I simulated the two multivibrator models in CMOS technology using the cadence tool. I was expecting the model 2 with Schmitt trigger(ST) will show robustness in PVT (Process Voltage temperature) ...
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Confusion regarding connecting nport in cadence while trying to find input impedance

I am a little bit confused on how to to connect the nport in the case where I try to find looking in impedance of a transmission line which is loaded by a 1pF capacitor on the one side. As shown in ...
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What is the equation for "beff", i.e., "Gain Factor in Saturation" in BSIM4?

Using the device parameter list in Cadence, I found out that ID follows this equation exactly: ID = 1/2 * beff * vgt**2 I also found out that ...
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2 answers
249 views

Designing Schmitt trigger oscillator using CMOS NAND gate

I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um ...
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3 votes
1 answer
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How to compare Matlab/Theory <=> Cadence: Switched-cap. Integrator: Mag & Phase

I tried to compare the simple switched-capacitor integrator below, between Cadence and Matlab (at the end acting as a simple loop-filter for a delta-sigma). I am stuck now on the point of how to ...
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VCO Tuning with MOSCAPs

I'm designing an integrated VCO for use in an FM Radio frequency PLL. In order to reduce the external part count, I had the idea of using MOSCAPs as the frequency tuning element instead of external ...
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PMOS Cascode (Virtuoso)

I have been given an assignment in which I have to implement a common source PMOS cascode (2 PMOS's above Vout, with upper one having the input voltage, and 2 NMOS's below Vout) using Cadence Virtuoso....
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Derivation of Parasitic capacitances in MOSFETs using Cadence Virtuoso

I have to design a circuit to derive the n-channel 180nm MOSFET gate-to-drain, and gate-to-source capacitances in Cadence virtuoso. I have little experience with the software, if someone could ...
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505 views

Among Cadence Virtuoso Calculator functions, is there a function that returns the y value when given an x value?

Among Cadence Virtuoso Calculator functions, is there a function that returns the y value when given an x value? I know the "cross" function can return the x value when given a y value. But ...
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1 answer
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Stability analysis of cross-coupled amplifier in Cadence

I am trying to implement a cross coupled amplifier with OP-AMP feedback. I am not able to get it stable for a square wave however. The circuit looks as follows: The OP AMP is ideal from Cadence, all ...
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Cadence gain and phase margin

I am trying to figure out the stability of an amplifier, for which I have to calculate the loop gain and make sure its not negative for instability. In Cadence one can use 'stb' analysis to calculate ...
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2 votes
1 answer
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What is no-probe-top in Cadence OrCAD

There is a rectangle around the outside of my OrCAD footprint (pointed to with the blue arrow), and it is on the no-probe-top layer. I googled it but I couldn't find any explanation of what that layer ...
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1 answer
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How do I delete wires in Cadence? [closed]

I'm losing my mind. I click delete, and try to select the wire and just can't do it. Nothing on the Internet explains it.
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232 views

How to specify the start up condition in an oscillator simulation using Cadence Virtuoso?

A real oscillator starts oscillating when there is some noise injected into its input. However, in Cadence virtuoso, how can I inject some noise into the input of the oscillator and make it oscillate?
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Cadence IC6.1.7 Installation

I want to install Cadence IC6.1.7 (Custom IC / Analog / RF Design) and Mentor Graphic Calibre tools on RHEL 8.2 server. I want to make the following things work after the installation: Circuit Design:...
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What are the essential layers in the design of a MOM capacitor in Cadence?

I need to design a custom-designed MOM capacitor. I have looked into the layout of a MOM capacitor in 65nm CMOS technology, and I am a bit confused. There are many layers that I don't understand the ...
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1 answer
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High Voltage NMOS layout design in UMC130nm process using Cadence Virtuoso

I am required to design an NMOS switch in UMC130nm process which is capable of enduring approximately 10V VDS (drain to source) when the gate is 0V. And a current of approximately 50mA when the gate ...
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buffered Op-amplifier

I am trying to simulate a buffer with an op-amp using CMOS, I am using Cadence. The phase margin I am getting is negative (not stable) about -272 deg, I am trying to reach 50 deg for a gain of 86 and ...
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voltage follower operational amplifier

I am trying to simulate a buffer with an op-amp using CMOS, I am using Cadence. The gain I am getting is low (16dB). I am trying to reach a gain of 90. how can I increase it? https://www.ti.com/lit/...
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CADENCE: layout error

I'm having problems contracting, in CADENCE for some modification that I can't use the layout, I normally did the INVERTER and AND ports, but when I get to the NAND port there are some errors, a ...
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