Questions tagged [cascode]
Anything related to cascode amplifier circuits. A cascode (not to be confounded with *cascade*) circuit is a two-stage direct-coupling amplifier topology using two amplifying elements (usually two BJTs or two FETs).
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Telescopic cascode amplifier design
I was following a tutorial from youtube and learning about double ended telescopic cascode 2 stage amplifiers. I was curious to know how to modify this circuit to get single ended zwo stage telescopic ...
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Designing a single ended Operational Transconductance
I am working on designing a single-ended Operational Transconductance Amplifier (OTA) with the following specifications in 180nm technology using LTspice:
DC Gain: > 65 dB
Unity Gain Bandwidth: >...
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THD of cascode emitter follower
I read an article about how the linearity of an emitter follower can be improved using a cascode configuration.
Here is the article: https://www.passlabs.com/technical_article/cascode-amp-design/
For ...
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Cascode transistor small signal analysis
I could not find a similar question on stack exchange and I need pretty urgent help.
I am confused about how to represent this circuit using small signal model for the transistors. Particularly R2, ...
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Best Technique to Find 'The' BJT For Your Circuit?
I'm working on a small high voltage cascode stack class A amplifier. The bandwidth is primarily limited by BJT capacitance. I have a working prototype, as well as a well defined LTSpice simulation.
My ...
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Why is my "common gate amplifier" introducing a zero when it shouldn't be introducing one as per theory?
I am trying to simulate a cascode circuit followed by a source follower in LTSpice and observe its frequency response. I added a 100GH inductor to serve as negative feedback only for DC, i.e., the ...
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Simple cascode biasing problem in an electronic circuit
use variable (𝐼_𝑅𝐸𝐹, 𝑉_𝑇𝐻,𝑉_𝐺𝑆) to express the range
Assume that all 4*(W/L)1= (W/L)2= (W/L)3= (W/L)4= (W/L)5= (W/L)6
All TRs are under saturation region
Assume that M2 is under subthreshold ...
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Output current increase in a cascode current mirror
I have been studying a cascode current mirror for an electronics class, that follows this configuration:
As I increase the output voltage Vd4, for most of the sweep the behavior is as expected, but ...
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cascode NMOS (virtuoso)
I have run across a problem.
When I was trying to design a cascode amplifier that was gain>=10V
I have succeeded to make it.
The rout in gm/Id method is 1.58M ohms.
When I typed the width and ...
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Instrumentation amplifier using folded cascode op-amp is not working
I made the sizing for a folded cascode operational amplifier, which is working well, however when I am trying to implement an instrumentation amplifier in LTspice using the blocks, it does not amplify ...
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How a cascode GaN can have a low Rds(on)?
GaN power device are said to have a lower Rds(ON) than Si MOSFET and according to the picture below there is no doubt about it.
Source: IEMN
Nevertheless as GaN power devices are particular devices, ...
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Floating Nodes in PSpice
Hello I am designing a folded cascode amplifier with only long channel devices. I believe I have set up the schematic correctly but I am getting the following errors:
ERROR(ORPSIM-15142): Node VB1 is ...
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Folded Cascode op-amp bias point
Below is a minimalistic schematic of a folded cascode op-amp input stage. The node Bias is usually drawn like a fixed voltage, which consequently makes the drain ...
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Wide Swing PMOS Cascode Biasing
I would like to know if someone has designed a wide swing PMOS cascode biasing circuit (as attached in the picture) in 16nm FinFET, especially for IO devices having 1.8V supply. I see that ...
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Why isn't my current mirror reflecting 500uA on each side?
I'm designing a telescopic cascode with a tail current source of 1mA. I had set my VDD to be 2V and all of the mosfets in the schematic seem to be saturated but the current reflected by the current ...
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How does one set the Q-point for a JFET cascode amplifier, and what are the correct "Idss" requirements for cascoded JFETs?
I am trying to teach myself electronics, and am currently attempting to learn about cascodes with the intent of building an RF amplifier that will amplify a microvolt signal up to line level with ...
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Amplitude shift keying using NMOS cascode transistor configuration
. I am using 50 MHz as a carrier signal and a pulse signal as the data signal. Unfortunately, I could not get my desired modulated ASK signal. I am using ADS software. Kindly guide me on how to do it. ...
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Cascode amplifier does not provide gain properly
I'm trying to build a Cascode amplifier on ads but I think I have a problem with my tank oscilator. Here's the complete circuit
The inductor is an air-core inductor from coilcraft and the transistor ...
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Role of input capacitance for cascode-input op-amp
In the below schematic of a cascode-input op-amp, the input transistors M1 and M2 present no capacitive load to the input signals, because their gate-source and gate-drain voltages are stabilized. The ...
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Is this cascoded opamp structure unstable by design (LTspice)?
I am playing with a cascode op-amp design and I have problems judging its stability (schematic at the end of the post).
When I judge the DC or AC analyses, it all looks good. No peaking and good phase ...
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Cascoded op-amp: What practically limits CMRR and input impedance?
I am interested to better understand the practical limitations to input impedance and common-mode rejection ratio in cascoded op-amp structures. I already simulated quite a bit, but I am running into ...
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Cascode: Which device goes into triode region first?
In the above cascode network, which device goes into triode region first, if the supply gradually decreases?
Framing the question other way round, if the supply gradually increases from 0V, which ...
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What is folded cascode? [duplicate]
What is a folded Cascode? I know what cascode topology is - but I cannot find good information about folded cascode? What is the difference?
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Finding the gain expression for this CMOS operational transconductance amplifier
So here's the circuit:
I think M2 is a common source amplifier and M4 a common gate amplifier, so they form a cascode amplifier where the gain is given by : Av = -gm2 * r0, r0 is the impedance at the ...
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Advice to calculate the transfer function of circuits
I'm a bit confused, to get the transfer function, what's the approach to work out in the cascade arranges like these?
I know it should be done using superposition, but passing R2 and cR3 I got lost ...
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Cascode BJT amplifier DC analysis assumption
simulate this circuit – Schematic created using CircuitLab
I am working on the DC analysis of a cascode amplifier.
If I assume base current is negligible I get the following equations:
From ...
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Voltage gain of PMOS differential telescopic cascode amplifier
I need help in understanding the function of the PMOS differential telescopic cascode amplifier.
For the NMOS counterpart, we are calculating the voltage gain as $$-g_{m1}{(g_{m3}r_{o1}+1)r_{o1} + r_{...
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Help Needed with LTSpice Multistage Cascode Simulation
I'm using this online calculator to get -50 gain for a cascode amplifier:
https://www.daycounter.com/Calculators/Cascode/BJT-Cascode-Calculator.phtml
However, I failed to duplicate the value in ...
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Audio Amplifier With MOSFET
I am working on a new project that seeks to implement a three-stage audio amplifier. One of my stages consists of a CASCODE circuit using the BF998 NMOS transistor. For this stage I am struggling to ...
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Controllable rising edge shifting circuit using CMOS
I am building a circuit using CMOS transistors (350n technology) in which I have to delay the rising edge of a pulse, but not the falling edge. The circuit I made is the following :
And here is the ...
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Designing a BJT cascode amplifier for decent gain and bandwidth
For my university course assignment I have to design a BJT amplifier using a Cascode stage with the following specifications using LTSpice. Only Vcc=3.3V and ground rails are available as well as a ...
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Design a cascode amplifier using suitable topology to meet the specifications (by varying W/L ratio) . VDD is 3.3 V
CONDITIONS:
Output swing has to be at-least 80% of VDD (> 2.64 V in this case).
Power supply rails available are VDD and ground only.
Only one current source can be used in the design; IREF = 50 ...
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Low-voltage cascode current mirror biasing circuit
On the left is a low voltage cascode current mirror and on the right is a circuit whose left branch generates \$V_b\$ for the mirror. Razavi (Design of Analog CMOS Integrated Circuits 2nd edition, ...
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Modulator design in ADS
hello everyone editing my previous post, i have biased my circuit now i want to run it for s-parameters simulation but when i attach term port it is giving a negative S(1,1).. any help would be ...
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Difference between MOSFET cascode and MOSFET in series
When using two MOSFETs in the cascode configuration the output resistance is approximated as gm × ro1 × ro2 where gm is the transconductance of the top device, ro1 the drain source resistance of the ...
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PMOS Cascode (Virtuoso)
I have been given an assignment in which I have to implement a common source PMOS cascode (2 PMOS's above Vout, with upper one having the input voltage, and 2 NMOS's below Vout) using Cadence Virtuoso....
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Find i/o pole of the cascade (BJT)
I have to obtain the pole of this circuit and the conversion function, but I can not do it .
How many poles does this circuit have?
And what are their relationships according to the arrangement of ...
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Equivalent resistance problem on cascode mirror circuit
I'm trying to analyze the cascode mirror, specifically its sensitivity to VCC variations.
Before facing with complicated calculations with the equivalent circuit, the tutorial (I'm following) ...
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How can I do a buffer to those circuit?
I need to project a amplifier with 3 stages. First, a differencial pair with active load and current mirror. Second, a cascode and third, a buffer. I'm using BC547(npn) for differencial pair and ...
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Definition of cascode?
What is the exact definition of cascode stage?
And can we regard this circuit as cascode?
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MOSFET cascode current
I have the following circuit:
I have two questions:
Is it possible to implement this circuit with non-matched MOSFET transistors?
How can I calculate the resistance to connect both in I_in and I_out?...
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Questions about cascode current mirror with MOSFETs
I have some queries related to this circuit:
Is there any way where we can implement it with non-matched MOS transistors?
If not, how do you calculate the I_output and I_ref relationship?
I am ...
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Question about cascode amplifier problem
The Rout in the circuit below is stated by my textbook to be Rout = [1 + gm2(r01||rπ2)]r02 + r01.
However, I thought the equation for Rout was Rout = [1 + gm2(r01||rπ2)]r02 + (r01||rπ2) for a cascode ...
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MOS Cascode - Shielding Property
I have some doubts trying to understand the "shielding" property of a cascode device.
I understand that a cascode provides a higher output resistance which can help to increase gain. However,...
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Cascode vs Folded-Cascode
I'm having a hard time understanding what the real benefit of a folded-cascode is over a simple cascode:
Also, one more question, is there any significance of there being a low-impedance node (source ...
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Signal clipping in cascade transistor amplifiers
The two-layer voltage amplifier circuit can transfer a signal of up to Vi = 50 mV to the output without clipping.and 1st stages gain Av1=-6.41 . +15 volt is ...
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Cascode Datasheet Capacitances
Cascode devices used in power systems are assigned values for Ciss, Coss and Crss in the datasheet, for example the UF3C120150K4S ( https://unitedsic.com/datasheets/DS_UF3C120150K4S.pdf )
What does ...
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How does JFET cascode amplifier reduce input capacitance?
I read that a JFET cascode amplifier has a reduced input capacitance thus lowering the Miller capacitance and will obtain wider bandwidth.
In order to obtain lower Miller cap, the voltage gain must ...
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Mid-band magnitude gain of a Cascode Amplifier
Looking to do some theoretical analysis on a Cascode Amplifier and compare it to a simulated model. Please see the circuit schematic below followed by the bode plot developed in the simulation ...
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Why cascode is not used often as a power switch
Say, we are building a synchronous buck and we have some beefy 600V 10A MOSFET, but it is not really suited for high frequency application - we need to be aware of dv/dt limits and it is hard to ...
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