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Questions tagged [chip-design]

Anything related to the design of integrated circuits (chips).

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What kind of PLL is typically used for the digital logic in high-frequency ASIC's? [closed]

Want to generate clocks up-to 2GHz from the PLL internal to the ASIC for the critical data-path logic, please advise. Thanks! Looks like there are wide variety of PLL's, dithered, multiphase, Fs, etc. ...
necro's user avatar
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23 votes
8 answers
6k views

How do computers prevent computational errors?

Say one transistor fails and causes the entire computation to be wrong, how does a computer check to see if it is correct? My only guess is that it does it multiple times across different units. I ...
Waterbloo's user avatar
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0 votes
1 answer
68 views

What is the need for implementing synthesizable linked list module in RTL?

Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs. Given that synthesized hardware has static memory size, what's the ...
HWDesigner's user avatar
15 votes
1 answer
2k views

What is the standard procedure for analogue IC tapeout?

This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
Jack Black's user avatar
0 votes
2 answers
98 views

"Click-to-reset and hold-to-bootloader" button design scheme for an ESP32-S3 development board design

I'm trying to design a development board using an ESP32-S3 MCU. The goal is to have the boot select button act as the lone button as well as do this with a completely analog design: When the ...
Gigoiy's user avatar
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5 votes
4 answers
527 views

When to have a pathway to ground in op-amp/comparator input?

When having a comparator IC, when should I put a resistor in series, to ground, or neither? I have three examples below: I understand ex1 may be useful to reduce offset voltage due to offset current. ...
ludicrous's user avatar
  • 1,163
0 votes
2 answers
53 views

Disconnecting load circuit from reference [current mirrors]

I have started learning microelectronics design and I am currently working on my bachelor thesis. There's one thing I wanted to ask you about current mirrors and its switching. My thesis is mainly ...
tom_ger's user avatar
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1 vote
2 answers
201 views

Ethernet MAC Controller IC design process

I'm from an embedded software background, and I am trying to learn more about chip design. To this end I want to understand what goes into designing and implementing a digital IC like an ethernet ...
NeedToKnow's user avatar
2 votes
1 answer
228 views

What are the difficulties in making e-beam lithography common? [closed]

3D printers are common and cheap. An e-beam lithographer doesn't seem much more difficult; laying down the photoresist seems pretty similar, and drawing lines with an e-beam doesn't seem very hard. ...
programjames's user avatar
0 votes
1 answer
51 views

Capacitances for inverter delay calculations

In CMOS VLSI DESIGN, Neil WESTE, page 144. "The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It ...
South goodman's user avatar
7 votes
2 answers
2k views

What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?

I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
Nadax's user avatar
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1 vote
3 answers
247 views

Why is the Vcc pin almost always next to the GND pin?

I have went through numerous times where the Vcc pin is shorted with the GND pin causing damage to the entire microcontroller, for example, pins 3 and 4 and pins 5 and 6 in the ATmega328P : Image ...
John Sall's user avatar
  • 251
2 votes
1 answer
153 views

How does Vds affect the overall transconductance of this OTA?

I am trying to determine the sizing of transistors in the OTA as shown below, using the gm/id methodology. I wanted gm1 and gm2 to have much larger gm than the other transistors to reduce noise. I ...
Jack Black's user avatar
4 votes
1 answer
265 views

What are the possible implementations of LUT on silicon?

I'm looking for the possible ways to implement a LUT. The only way I know is to use Flip Flops to store the outputs and a MUX to select the output using the input as a select signal. Is there any ...
Hmdee's user avatar
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0 votes
4 answers
969 views

What is the reason some microcontrollers are designed to be powered with 5V or 3.3V while the most common battery is 3.7V? [duplicate]

As we know, most batteries' voltage is rated 1.5V (alkaline) and 3.7V (Li-Ion). Indeed, alkaline battery will be 1.65V when it is new, while Li-Ion can reach 4.2V when it is fully charged. Most ...
AirCraft Lover's user avatar
0 votes
2 answers
225 views

Does my schematic look correct? (Double check)

I am a complete beginner when it comes to creating schematics and PCBs. I also don't know if this is the right place to ask this question, because I am also pretty new to writing forum entries. I have ...
Y-E-Quit's user avatar
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1 vote
2 answers
222 views

What's wrong with this CMOS implementation of XOR?

I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My first attempt had floating nodes and other issues with untethered ...
Connor's user avatar
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6 votes
2 answers
2k views

Why is this CMOS implementation of XOR wrong?

I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My attempt at this is the following: The given answer is this: Why is ...
Connor's user avatar
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0 votes
1 answer
112 views

Standard cell design flow in an ASIC design flow

I have a question regarding the standard cell design flow in an ASIC design flow. That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
patvax's user avatar
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0 votes
1 answer
111 views

Feasibility of building a benchtop chip fab for prototyping

This is generally quite a vague question as I'm new to the space but I've been thinking a lot about prototyping in the IC/semiconductor space and have been wondering about the feasibility of ...
sam's user avatar
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1 vote
1 answer
524 views

Verilog code execution in gate level modeling

The following is Verilog code an SR latch. ...
PG1995's user avatar
  • 245
0 votes
1 answer
71 views

Lead width range for motor driver IC

I am creating a footprint for this part in Altium. I was able to get all the dimensions, but can't seem to figure out the lead width range as shown in this diagram: I was wondering if anyone could ...
Marko Jurisic's user avatar
-1 votes
1 answer
67 views

What design changes are made for automotive or XT versions of chips?

I'm interested in what design changes are required to support wildly different temperature tolerances. Take for example the following 3 chips: Nearly identical in form and function, package design, ...
Ron Beyer's user avatar
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0 votes
1 answer
509 views

Why is it necessary that the poly line extends the diffusion strip in a layout?

Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
Essam's user avatar
  • 337
3 votes
2 answers
2k views

Why aren't aluminum and nitrogen used as dopants in semiconductors, chips, etc.?

Boron is most commonly used for the p-type dopant, and phosphorus for the n-type, correct? Why not aluminum for the p-type and nitrogen for the n-type? Is it just a matter of cost and/or convenience?
Kurt Hikes's user avatar
0 votes
1 answer
309 views

Can't set clock network delay to zero during synthesis

I am using Synopsys Design Compiler for synthesizing my design. I have read in the User's guide of DC that by default it assumes ideal clocking during synthesis meaning that clocks have zero network ...
O'ara's user avatar
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0 votes
1 answer
34 views

Clock network remains at x when applying fast clock frequencies

I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of ...
O'ara's user avatar
  • 1
31 votes
4 answers
6k views

Why are most COB LEDs physically yellow?

Many "LEDs" found on devices nowadays appear to be yellow where the light comes from (when the device is off). Why yellow? I put LEDs in quotes because COB leds can consist of many ...
Bort's user avatar
  • 5,182
1 vote
2 answers
2k views

ASIC gate count estimation and SRAM vs flip-flops

I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand. Logic gates Two ...
ozne's user avatar
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3 votes
2 answers
4k views

Which software is used to design (and simulate) IC?

Currently I'm using Proteus to design and simulate all of my schematics. Is there any (free) software for designing and simulating ICs? I searched the Internet and found Cadence and Glade Thanks!
raspiduino's user avatar
3 votes
3 answers
3k views

Whats the cost to create your own custom ASIC chip? [closed]

There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
kenny alves's user avatar
1 vote
2 answers
878 views

Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
Carter's user avatar
  • 619
3 votes
1 answer
1k views

How dense is SRAM compared to random logic?

Modern CPUs always have some on-chip cache, typically more than one level. This takes a lot of die area; static RAM is generally reckoned at six transistors per bit. That having been said, the ...
rwallace's user avatar
  • 563
26 votes
15 answers
12k views

Is there a theoretical possibility of having a full computer on a silicon wafer instead of a motherboard?

I have not seen a single reference where a whole computer is built inside a chip itself instead of modularizing and spreading it on a board. I acknowledge that having modular parts enable versatility, ...
user0193's user avatar
  • 436
2 votes
2 answers
893 views

Can drain and source length be smaller than minimum channel length in CMOS technology?

I know the channel width can't be smaller, but what about drain and source? Say, in 0.18u technology, what would be a typical drain/source length?
MNaz's user avatar
  • 215
1 vote
1 answer
105 views

What is difference between MOSIS and dedicate MPW services of foundries?

Most foundries, such as TSMC, SMICS, and Samsung have MPW and IC prototyping services. What is the difference between these services and MOSIS or Europractice? Question is: Why use MOSIS services ...
Bright Day's user avatar
6 votes
4 answers
3k views

Why is the 8061 microcontroller described as having 256 bytes of internal memory?

According to doc (http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf), this 8061 microprocessor chip contains 256bytes of internal RAM (also referred to as register file in the doc). However, the ...
Jt90's user avatar
  • 71
5 votes
1 answer
801 views

Why are photomasks so expensive?

I just read the answer to this question asking how much a custom ASIC costs. It says that When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (...
user avatar
0 votes
2 answers
109 views

Is integrated circuit packaging copyrighted/patented? [closed]

A friend of mine is interested in manufacturing ICs. He wants to know whether the different form types of packages (DIP, LGA, BGA) have intellectual property obstacles to using them. If so, who owns ...
Larry B.'s user avatar
  • 103
0 votes
1 answer
389 views

Are there technical documents about microprocessor design by Jim Keller? [closed]

Jim Keller has worked leading various chip design projects at Intel, AMD, Apple and Tesla among other companies. Does anybody know of any technical documents about microprocessor design written by ...
Ken Grimes's user avatar
  • 1,309
3 votes
1 answer
7k views

Difference between the words 'die' and 'chip' [closed]

In some articles speaking about the IGBT power modules, we can see that the word 'die' has been used for calling the semiconductor component of IGBT device. However, other articles calls it 'chip'. ...
Albert's user avatar
  • 151
1 vote
0 answers
173 views

IGBT chip metalization

Consider an IGBT chip within a power module. The top surface of the chip is often metalized by aluminum (with approximately 5 microns thickness) to bond some aluminum wires into the chip; I am hazy ...
Albert's user avatar
  • 151
0 votes
1 answer
368 views

Are 7nm or 10nm transistors reality or is it just a marketing strategy by processor manufacturers?

Now a days chip manufacturers, like Qualcomm, claim that they have built a 7nm chip. Is 7nm really the size of transistor or is it just a marketing strategy? If 7nm is just for marketing and not the ...
Jak Ahmed's user avatar
1 vote
1 answer
167 views

How the Cerebras across the reticle limits to produce the largest chip,WSE?

How are the connections made on wafer-scale circuits (50,000 mm2 and up), given that the imaging reticle limits are around 600 to 800 mm2?
Jane Cai's user avatar
1 vote
2 answers
346 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
seyyedali hosseini's user avatar
0 votes
1 answer
148 views

Zero Voltage in a power semiconductor chip

In an ON-mode silicon IGBT chip operating within a real power module, is the collector contact fixed at 0 V or emitter? What about Power SiC MOSFET? enter link description here
Albert's user avatar
  • 151
0 votes
2 answers
82 views

Addressing 45 Inputs Down to 6 pin Output

I'm looking for a chip which could minimize ~45 button inputs down to an 6 pin input for use with Raspberry Pi. I know this is a simple problem and it has likely been solved before, but as an ...
DHLaurelT's user avatar
0 votes
1 answer
77 views

Are there ways/technologies to use High negative voltages in flash memories?

I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything ...
ElecNoob's user avatar
3 votes
2 answers
169 views

What is this? Identifying Proximity Sensor Chip (IR)

I am in a bit of a pickle. If anyone could help/has any ideas I will be very grateful - am aware this post is pretty long but thought if anyone was clever enough to know it would be you guys. If ...
Calum Nicoll's user avatar
24 votes
3 answers
9k views

Why are chip designers called "triangle pushers"?

I heard chip designers being described as "triangle pushers," the idea being that somehow the logic on the chip was formulated by arranging triangles on the silicon in certain ways. How does this work?...
Tyler Durden's user avatar
  • 2,206