Questions tagged [chip-design]
Anything related to the design of integrated circuits (chips).
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Verilog code execution in gate level modeling
The following is Verilog code an SR latch.
...
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Lead width range for motor driver IC
I am creating a footprint for this part in Altium. I was able to get all the dimensions, but can't seem to figure out the lead width range as shown in this diagram:
I was wondering if anyone could ...
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What design changes are made for automotive or XT versions of chips?
I'm interested in what design changes are required to support wildly different temperature tolerances. Take for example the following 3 chips:
Nearly identical in form and function, package design, ...
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Why is it necessary that the poly line extends the diffusion strip in a layout?
Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
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Why aren't aluminum and nitrogen used as dopants in semiconductors, chips, etc.?
Boron is most commonly used for the p-type dopant, and phosphorus for the n-type, correct?
Why not aluminum for the p-type and nitrogen for the n-type?
Is it just a matter of cost and/or convenience?
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Can't set clock network delay to zero during synthesis
I am using Synopsys Design Compiler for synthesizing my design. I have read in the User's guide of DC that by default it assumes ideal clocking during synthesis meaning that clocks have zero network ...
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Clock network remains at x when applying fast clock frequencies
I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of ...
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How to make diodes and bonding pads in Electric (ID design program)?
I'm a beginner user of Electric, a free VLSI/IC design program.
Let me preface, that the last time I've used an IC design program was nine years ago at University. We used Cadence Virtuoso back then. ...
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Why are most COB LEDs physically yellow?
Many "LEDs" found on devices nowadays appear to be yellow where the light comes from (when the device is off). Why yellow?
I put LEDs in quotes because COB leds can consist of many ...
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ASIC gate count estimation and SRAM vs flip-flops
I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration.
Below is what I found out. Please feel free to correct, comment, expand.
Logic gates
Two ...
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Which software is used to design (and simulate) IC?
Currently I'm using Proteus to design and simulate all of my schematics. Is there any (free) software for designing and simulating ICs? I searched the Internet and found Cadence and Glade Thanks!
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Whats the cost to create your own custom ASIC chip? [closed]
There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?
I've been studying to understand Static Timing Analysis aka STA.
One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
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How dense is SRAM compared to random logic?
Modern CPUs always have some on-chip cache, typically more than one level. This takes a lot of die area; static RAM is generally reckoned at six transistors per bit.
That having been said, the ...
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Is there a theoretical possibility of having a full computer on a silicon wafer instead of a motherboard?
I have not seen a single reference where a whole computer is built inside a chip itself instead of modularizing and spreading it on a board.
I acknowledge that having modular parts enable versatility, ...
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Can drain and source length be smaller than minimum channel length in CMOS technology?
I know the channel width can't be smaller, but what about drain and source? Say, in 0.18u technology, what would be a typical drain/source length?
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Comparing two hardware accelerators with different number of MAC units
I am a software engineer but am admittedly a bit of a noob on the device side of things.
I am wondering how to compare two chips. Let's say both chips have hardware accelerator components. Only thing ...
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Can someone give me feedback about this adjustable floating voltage reference?
I am not sure actually with the name of the circuit so excuse me if the naming is not accurate.
What I am trying to make is I want to have an adjustable output voltage whose reference can be adjusted ...
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What is difference between MOSIS and dedicate MPW services of foundries?
Most foundries, such as TSMC, SMICS, and Samsung have MPW and IC prototyping services.
What is the difference between these services and MOSIS or Europractice?
Question is:
Why use MOSIS services ...
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Why is the 8061 microcontroller described as having 256 bytes of internal memory?
According to doc (http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf), this 8061 microprocessor chip contains 256bytes of internal
RAM (also referred to as register file in the doc). However, the ...
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Why are photomasks so expensive?
I just read the answer to this question asking how much a custom ASIC costs. It says that
When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (...
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Is integrated circuit packaging copyrighted/patented? [closed]
A friend of mine is interested in manufacturing ICs. He wants to know whether the different form types of packages (DIP, LGA, BGA) have intellectual property obstacles to using them. If so, who owns ...
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Are there technical documents about microprocessor design by Jim Keller? [closed]
Jim Keller has worked leading various chip design projects at Intel, AMD, Apple and Tesla among other companies.
Does anybody know of any technical documents about microprocessor design written by ...
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Difference between the words 'die' and 'chip' [closed]
In some articles speaking about the IGBT power modules, we can see that the word 'die' has been used for calling the semiconductor component of IGBT device. However, other articles calls it 'chip'. ...
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IGBT chip metalization
Consider an IGBT chip within a power module.
The top surface of the chip is often metalized by aluminum (with approximately 5 microns thickness) to bond some aluminum wires into the chip; I am hazy ...
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Junction Temperature Estimation Error
When predicting the junction temperature (Tj) of semiconductor chips (for example IGBTs) by available thermal models such as FEM simulations, how much is the maximum permissible Tj estimation error ...
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Are 7nm or 10nm transistors reality or is it just a marketing strategy by processor manufacturers?
Now a days chip manufacturers, like Qualcomm, claim that they have built a 7nm chip. Is 7nm really the size of transistor or is it just a marketing strategy? If 7nm is just for marketing and not the ...
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How the Cerebras across the reticle limits to produce the largest chip,WSE?
How are the connections made on wafer-scale circuits (50,000 mm2 and up), given that the imaging reticle limits are around 600 to 800 mm2?
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CMOS technology that works above 300 °C
I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect.
Do foundries like TSMC or Globalfoundries ...
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Zero Voltage in a power semiconductor chip
In an ON-mode silicon IGBT chip operating within a real power module, is the collector contact fixed at 0 V or emitter?
What about Power SiC MOSFET?
enter link description here
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Addressing 45 Inputs Down to 6 pin Output
I'm looking for a chip which could minimize ~45 button inputs down to an 6 pin input for use with Raspberry Pi.
I know this is a simple problem and it has likely been solved before, but as an ...
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Temperature-dependent leakage current in IGBTs
On one hand, the leakage current of power electronics modules such as IGBTs depends on the temperature. On the other hand, the temperature distribution on the IGBT chips is significantly non-uniform ...
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Are there ways/technologies to use High negative voltages in flash memories?
I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything ...
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What is this? Identifying Proximity Sensor Chip (IR)
I am in a bit of a pickle. If anyone could help/has any ideas I will be very grateful - am aware this post is pretty long but thought if anyone was clever enough to know it would be you guys. If ...
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Non-uniform temperatue distribution
Please assume a semiconductor chip like IGBT or MOSFET heated by a specific power loss. It is found that the more the power loss is, the more severe the chip's temperature distribution non-uniformity ...
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Uneven chip temperature
When injecting a uniform power dissipation in a chip of IGBT power electronics modules by finite element method (FEM) in COMSOL (a good software for thermal analysis), a non-uniform temperature ...
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Why are chip designers called "triangle pushers"?
I heard chip designers being described as "triangle pushers," the idea being that somehow the logic on the chip was formulated by arranging triangles on the silicon in certain ways. How does this work?...
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Good practices for full-custom IC measurement? [closed]
I am a Junior Analog IC Designer and I want to characterize a full-custom IC. The thing is that I want to do it well and I don't know any reference with good practices and PCB design guidelines for ...
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In modern CPUs, is the etched chip face-up in the packaging?
I know that the integrated circuits of the 1980s had the etched chip glued face-up inside the packaging, with tiny gold wires bridging the open space from the top surface of the chip, down to contact ...
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How do I attach an IC chip to a DIN rail? [closed]
I am using a 74AHCT125N to shift up voltage of pwm signal. The problem we are having is how to attach this chip to DIN rail. We were thinking of using a DIN rail mounted PCB. I am looking for ...
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QFN-like package identification
Can anybody identify this package? Looks like a sort of QFN to me but it's not square and I have not been able to find anything like it.
The chip itself is proprietary, no datasheet available for it.
...
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What is standard about standard cells in layout designing? [closed]
Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
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Design of 7400 Series IC
Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
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PN53x with emulate nfc
I saw that many of nfc reader/emulate based on PN53x chipset of NXP.
But the disadvantage of this chipset is , you can't emulate ISO14443-B
why is PN53x chipset ...
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GDSII stream reading
GDSII is a photomask\artwork format for photolitography. I am having trouble resolving a particular line in the file.
For example, 'SRefs' means it refers to one of the structures and uses this ...
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Is VHDL for digital circuits only?
Both Wikipedia and other SO questions about VHDL vs Verilog mention digital when describing VHDL.
Can you use VHDL to design analog circuits?
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How does the IC design process work? [closed]
Particularly for highly complex, digital ICs. Is it bottom up or top down? In particular, for top-down design designs the actual logic gates?
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What is the structural difference between a high-drive and a low-drive cell?
I've come across IC's that are labeled high-drive and low drive. I know that a high-drive IC has a higher intrinsic propagation delay but isn't as steep as a low-drive IC in function of the load to ...
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Difference between a memory cell and a memory chip?
I have gotten very confused on the fundamentals of computer memory in regards to memory cells and chips. I have been reading Assembly Language Step By Step Programming with Linux by Jeff Duntemann and ...
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Voltage conversion +1V to -3V inside a new IC design
I am looking for a good integrated CMOS solution for creating -3V out of a 1V supply. The -3V are just used for biasing and hence do not load the supply.
This means that the solution should be switch ...