Questions tagged [chip-design]

Anything related to the design of integrated circuits (chips).

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What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?

I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
Nadax's user avatar
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How can retrive the localtion maximum of an array in hardware design

Suggesting a 200*200 array (Matrix) of registers, which contains unsigned integers. Is there a better way to locate the maximum number rather than find the maximum and binary search: O(n)* ADC time It'...
Leo's user avatar
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1 vote
3 answers
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Why is the Vcc pin almost always next to the GND pin?

I have went through numerous times where the Vcc pin is shorted with the GND pin causing damage to the entire microcontroller, for example, pins 3 and 4 and pins 5 and 6 in the ATmega328P : Image ...
John Sall's user avatar
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Microstrip feeds for silicon spiral inductor

I have a question about spiral inductors used in CMOS. If we feed a spiral inductor with microstrip feedlines, won't (most of) the signal simply reflect away from the inductor since there is no ...
Balram G Pillai's user avatar
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CPU's ESD Rating

Today I was assembling a PC, and went through all the ESD stuff but at the end was wondering how sensitive are these devices actually are. So my question is What is the ESD HBM rating of a CPU pins ...
pazel1374's user avatar
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2 votes
1 answer
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How does Vds affect the overall transconductance of this OTA?

I am trying to determine the sizing of transistors in the OTA as shown below, using the gm/id methodology. I wanted gm1 and gm2 to have much larger gm than the other transistors to reduce noise. I ...
George Guo's user avatar
4 votes
1 answer
249 views

What are the possible implementations of LUT on silicon?

I'm looking for the possible ways to implement a LUT. The only way I know is to use Flip Flops to store the outputs and a MUX to select the output using the input as a select signal. Is there any ...
Hmdee's user avatar
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4 answers
562 views

What is the reason some microcontrollers are designed to be powered with 5V or 3.3V while the most common battery is 3.7V? [duplicate]

As we know, most batteries' voltage is rated 1.5V (alkaline) and 3.7V (Li-Ion). Indeed, alkaline battery will be 1.65V when it is new, while Li-Ion can reach 4.2V when it is fully charged. Most ...
AirCraft Lover's user avatar
0 votes
2 answers
192 views

Does my schematic look correct? (Double check)

I am a complete beginner when it comes to creating schematics and PCBs. I also don't know if this is the right place to ask this question, because I am also pretty new to writing forum entries. I have ...
Y-E-Quit's user avatar
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1 vote
2 answers
169 views

What's wrong with this CMOS implementation of XOR?

I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My first attempt had floating nodes and other issues with untethered ...
Connor's user avatar
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6 votes
2 answers
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Why is this CMOS implementation of XOR wrong?

I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My attempt at this is the following: The given answer is this: Why is ...
Connor's user avatar
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0 answers
342 views

What are pre-driver and driver circuits in an IC?

I'm new to analog IC design. What does a pre-driver or driver circuit look like, and what is their main function?
Callum Ormond's user avatar
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Capacitors in the path of power and ground

Is there any risk of using capacitors or decoupling capacitors directly between a top level power supply and Vss? The electrical rule checks don't propagate voltage through capacitors so this issue of ...
Alan Saldanha's user avatar
0 votes
1 answer
78 views

Standard cell design flow in an ASIC design flow

I have a question regarding the standard cell design flow in an ASIC design flow. That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
patvax's user avatar
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1 answer
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Feasibility of building a benchtop chip fab for prototyping

This is generally quite a vague question as I'm new to the space but I've been thinking a lot about prototyping in the IC/semiconductor space and have been wondering about the feasibility of ...
sam's user avatar
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1 answer
335 views

Verilog code execution in gate level modeling

The following is Verilog code an SR latch. ...
PG1995's user avatar
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1 answer
67 views

Lead width range for motor driver IC

I am creating a footprint for this part in Altium. I was able to get all the dimensions, but can't seem to figure out the lead width range as shown in this diagram: I was wondering if anyone could ...
Marko Jurisic's user avatar
-1 votes
1 answer
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What design changes are made for automotive or XT versions of chips?

I'm interested in what design changes are required to support wildly different temperature tolerances. Take for example the following 3 chips: Nearly identical in form and function, package design, ...
Ron Beyer's user avatar
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Why is it necessary that the poly line extends the diffusion strip in a layout?

Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
Essam's user avatar
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3 votes
2 answers
1k views

Why aren't aluminum and nitrogen used as dopants in semiconductors, chips, etc.?

Boron is most commonly used for the p-type dopant, and phosphorus for the n-type, correct? Why not aluminum for the p-type and nitrogen for the n-type? Is it just a matter of cost and/or convenience?
Kurt Hikes's user avatar
0 votes
1 answer
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Can't set clock network delay to zero during synthesis

I am using Synopsys Design Compiler for synthesizing my design. I have read in the User's guide of DC that by default it assumes ideal clocking during synthesis meaning that clocks have zero network ...
O'ara's user avatar
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1 answer
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Clock network remains at x when applying fast clock frequencies

I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of ...
O'ara's user avatar
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31 votes
4 answers
5k views

Why are most COB LEDs physically yellow?

Many "LEDs" found on devices nowadays appear to be yellow where the light comes from (when the device is off). Why yellow? I put LEDs in quotes because COB leds can consist of many ...
Bort's user avatar
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1 vote
2 answers
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ASIC gate count estimation and SRAM vs flip-flops

I'd like to be able to estimate gate counts of different designs for the purpose of architectural exploration. Below is what I found out. Please feel free to correct, comment, expand. Logic gates Two ...
ozne's user avatar
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3 votes
2 answers
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Which software is used to design (and simulate) IC?

Currently I'm using Proteus to design and simulate all of my schematics. Is there any (free) software for designing and simulating ICs? I searched the Internet and found Cadence and Glade Thanks!
raspiduino's user avatar
1 vote
3 answers
2k views

Whats the cost to create your own custom ASIC chip? [closed]

There are never any bitcoin miners available to purchase and whenever Bitmain (the leading bitcoin mining manufacturer) releases a new batch of miners they all get gobbled up in seconds. For those who ...
kenny alves's user avatar
1 vote
2 answers
661 views

Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
Carter's user avatar
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3 votes
1 answer
992 views

How dense is SRAM compared to random logic?

Modern CPUs always have some on-chip cache, typically more than one level. This takes a lot of die area; static RAM is generally reckoned at six transistors per bit. That having been said, the ...
rwallace's user avatar
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24 votes
15 answers
12k views

Is there a theoretical possibility of having a full computer on a silicon wafer instead of a motherboard?

I have not seen a single reference where a whole computer is built inside a chip itself instead of modularizing and spreading it on a board. I acknowledge that having modular parts enable versatility, ...
user0193's user avatar
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2 votes
2 answers
693 views

Can drain and source length be smaller than minimum channel length in CMOS technology?

I know the channel width can't be smaller, but what about drain and source? Say, in 0.18u technology, what would be a typical drain/source length?
MNaz's user avatar
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Comparing two hardware accelerators with different number of MAC units

I am a software engineer but am admittedly a bit of a noob on the device side of things. I am wondering how to compare two chips. Let's say both chips have hardware accelerator components. Only thing ...
Jenna Kwon's user avatar
1 vote
0 answers
104 views

Can someone give me feedback about this adjustable floating voltage reference?

I am not sure actually with the name of the circuit so excuse me if the naming is not accurate. What I am trying to make is I want to have an adjustable output voltage whose reference can be adjusted ...
Codelearner777's user avatar
1 vote
1 answer
97 views

What is difference between MOSIS and dedicate MPW services of foundries?

Most foundries, such as TSMC, SMICS, and Samsung have MPW and IC prototyping services. What is the difference between these services and MOSIS or Europractice? Question is: Why use MOSIS services ...
Bright Day's user avatar
6 votes
4 answers
3k views

Why is the 8061 microcontroller described as having 256 bytes of internal memory?

According to doc (http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf), this 8061 microprocessor chip contains 256bytes of internal RAM (also referred to as register file in the doc). However, the ...
Jt90's user avatar
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5 votes
1 answer
616 views

Why are photomasks so expensive?

I just read the answer to this question asking how much a custom ASIC costs. It says that When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (...
user avatar
0 votes
2 answers
106 views

Is integrated circuit packaging copyrighted/patented? [closed]

A friend of mine is interested in manufacturing ICs. He wants to know whether the different form types of packages (DIP, LGA, BGA) have intellectual property obstacles to using them. If so, who owns ...
Larry B.'s user avatar
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0 votes
1 answer
365 views

Are there technical documents about microprocessor design by Jim Keller? [closed]

Jim Keller has worked leading various chip design projects at Intel, AMD, Apple and Tesla among other companies. Does anybody know of any technical documents about microprocessor design written by ...
Ken Grimes's user avatar
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3 votes
1 answer
6k views

Difference between the words 'die' and 'chip' [closed]

In some articles speaking about the IGBT power modules, we can see that the word 'die' has been used for calling the semiconductor component of IGBT device. However, other articles calls it 'chip'. ...
Albert's user avatar
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1 vote
0 answers
157 views

IGBT chip metalization

Consider an IGBT chip within a power module. The top surface of the chip is often metalized by aluminum (with approximately 5 microns thickness) to bond some aluminum wires into the chip; I am hazy ...
Albert's user avatar
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0 votes
0 answers
45 views

Junction Temperature Estimation Error

When predicting the junction temperature (Tj) of semiconductor chips (for example IGBTs) by available thermal models such as FEM simulations, how much is the maximum permissible Tj estimation error ...
Albert's user avatar
  • 149
0 votes
1 answer
326 views

Are 7nm or 10nm transistors reality or is it just a marketing strategy by processor manufacturers?

Now a days chip manufacturers, like Qualcomm, claim that they have built a 7nm chip. Is 7nm really the size of transistor or is it just a marketing strategy? If 7nm is just for marketing and not the ...
Jak Ahmed's user avatar
1 vote
1 answer
125 views

How the Cerebras across the reticle limits to produce the largest chip,WSE?

How are the connections made on wafer-scale circuits (50,000 mm2 and up), given that the imaging reticle limits are around 600 to 800 mm2?
Jane Cai's user avatar
1 vote
2 answers
334 views

CMOS technology that works above 300 °C

I need technology in which the IC will work at temperatures above 300 °C. For example, Fraunhofer makes chips at this temperature using Tungsten interconnect. Do foundries like TSMC or Globalfoundries ...
seyyedali hosseini's user avatar
0 votes
1 answer
147 views

Zero Voltage in a power semiconductor chip

In an ON-mode silicon IGBT chip operating within a real power module, is the collector contact fixed at 0 V or emitter? What about Power SiC MOSFET? enter link description here
Albert's user avatar
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0 votes
2 answers
82 views

Addressing 45 Inputs Down to 6 pin Output

I'm looking for a chip which could minimize ~45 button inputs down to an 6 pin input for use with Raspberry Pi. I know this is a simple problem and it has likely been solved before, but as an ...
DHLaurelT's user avatar
0 votes
0 answers
93 views

Temperature-dependent leakage current in IGBTs

On one hand, the leakage current of power electronics modules such as IGBTs depends on the temperature. On the other hand, the temperature distribution on the IGBT chips is significantly non-uniform ...
Albert's user avatar
  • 149
0 votes
1 answer
69 views

Are there ways/technologies to use High negative voltages in flash memories?

I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything ...
ElecNoob's user avatar
3 votes
2 answers
156 views

What is this? Identifying Proximity Sensor Chip (IR)

I am in a bit of a pickle. If anyone could help/has any ideas I will be very grateful - am aware this post is pretty long but thought if anyone was clever enough to know it would be you guys. If ...
Calum Nicoll's user avatar
0 votes
0 answers
51 views

Non-uniform temperatue distribution

Please assume a semiconductor chip like IGBT or MOSFET heated by a specific power loss. It is found that the more the power loss is, the more severe the chip's temperature distribution non-uniformity ...
Mohsen's user avatar
  • 49
0 votes
0 answers
66 views

Uneven chip temperature

When injecting a uniform power dissipation in a chip of IGBT power electronics modules by finite element method (FEM) in COMSOL (a good software for thermal analysis), a non-uniform temperature ...
Mohsen's user avatar
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