Stack Exchange Network

Stack Exchange network consists of 174 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

0
votes
1answer
67 views

Clock oscillator pin, requirement, ac-decoupling and termination

I'm trying to make something with ADI PLL (ADF4159 and ADF5901). In their datasheet there is nothing about how to source the clock pin. I have found lots of information about clocks on the internet ...
0
votes
1answer
65 views

What are the advantages of a wider bus in comparison to those of a higher clock frequency? [on hold]

The aim is to increase data transfer rate. I understand each may have some drawbacks and advantages. Frankly I'm not knowledgeable enough to know of many so I'd like some input from others. I know ...
0
votes
0answers
30 views

Clock source switching

I am designing Main board using Altera FPGA. In circuit I need external differential clock. On main board I have introduce one clock generator circuit also have provision to take clock from external ...
1
vote
1answer
30 views

Clock signal purpose

I'm a mechE and have been trying to get into the digital world for a bit and need to know why a system would need a clock signal at all. For example, if I have some bit of code getting executed on a ...
1
vote
1answer
48 views

CPU clock cycles required to execute the following inx?

Consider the following data path of a simple non-pipelined CPU. The registers A,B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8×(2:1) and the ...
1
vote
2answers
103 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
2
votes
1answer
35 views

Selecting the equipment with the optimal 10 MHz reference

In a larger testbench I have 5 synchronized instruments (signal generators, ARBs, VSAs etc). I am trying to decide which instrument to take as "master". I rule out the older/cheaper parts (Tektronix ...
2
votes
2answers
47 views

10 MHz reference distribution (daisy chaining vs. BNC tees vs something else)

10 MHz is the quasi-standard for reference clock in measurement equipment. Most boxes have "REF in" and "REF out" or "10 MHz in"/"10 MHz out". In my case, I have a measurement setup consisting of an ...
0
votes
0answers
27 views

Can this circuit produce 0, 5 and 12 volts in fixed increments for the AT89LP4052?

Due to the speed requirements of my project, I'm looking at replacing the AT89C4051 with an AT89LP4052 with some code modifications since it offers double the memory and 6x the speed for the same ...
0
votes
1answer
37 views

IN/OUT pin of the crystal circuits [duplicate]

Got few questions about the input/output pins of a crystal circuit. As shown above, it's a common clock circuits. My question is: 1. If we want to measure the waveform of the clock, which pin should ...
0
votes
2answers
53 views

How to limit the output voltage of a TCXO?

I am using an SiT1552 MEMS TCXO providing 32.768 kHz. It will be sourcing two ICs: a microcontroller and a DA14580 Bluetooth Low Energy transceiver. The ICs and TCXO are all powered by 3.3V. The TCXO ...
0
votes
1answer
43 views

Crystal reference and capacitors for w5500

I'm selecting the caps for the crystal oscillator of the wiznet W5500. The standard Load Capacitance for 25Mhz crystals is 18pF. I found out that the hardware guideline claims for a Load Capacitance ...
2
votes
1answer
64 views

Quartz Clock Accuracy

Do the vibrations of aircraft engines (or any engine, for that matter) dilute the accuracy of a quartz clock? I haven't done any kind of research or hypothesis testing, though I believe that the ...
0
votes
0answers
73 views

Connecting an adc to a microcontroller

In a previous post, where my problem was to find the right adc to convert an ananlog signal at 4 MHz speed. I've been recommended the ADC 1175 which samples at 20 Msps minimum. Fine. And since it ...
1
vote
2answers
99 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
0
votes
3answers
83 views

How can I see an output from SCL?

I am new to electronics, circuits, etc. Currently I am reading I2C and synchronous serial communications. As I understand, two devices must be connected to the same CLOCK wire so that the slave knows ...
1
vote
1answer
36 views

LCD SPI clock frequency with STM32L0 MCU

I'm designing a PCB that includes LCD Display NHD-C12832A1Z-FSW-FBW-3V3 (datasheet) connected to the STM32L071KZU6 microcontroller (datasheet). I'm afraid that the SPI interface of the LCD will not ...
4
votes
2answers
126 views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
0
votes
1answer
76 views

How do I redirect/regenerate an input clock to an output pin in my FPGA design (Verilog)

I've got an ADC that requires me to send it 20 clock pulses when requesting to read data out of its internal register (after I've triggered it to read data from my sensor). I was able to simulate ...
5
votes
4answers
2k views

Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external crystal?

I'm building a circuit that I'd like to run at 8 MHz to begin with, but I want to be able to try it out at 10, 12, 16, 20, and, maybe, 25 MHz. I know that many microcontrollers have the ability to ...
0
votes
1answer
102 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
15
votes
2answers
4k views

Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge?...
6
votes
3answers
815 views

gps performance for synchronization

I can't understand why GPS reciever clock is very good (stratum 0). I know it's very accurate and pure within itself; but when it passes through a long distance wireless channel, then it has low power ...
2
votes
2answers
123 views

Crystals, capacitors and W5100

Background: I have built a number of devices based on the W5100 chip, all them were (are) working more or less decently. However last batch currently in testing show faulty behavior - almost all of ...
0
votes
2answers
99 views

Change a quartz clock timebase by changing the frequency of the quartz crystal oscillator?

I've been doing some research on rewiring clock circuits for a project, but I'm new to these types of pulse-counting circuits. My question at this point is: If I replace the existing quartz crystal ...
5
votes
2answers
727 views

How to get 8MHz square signal out a pic18f45

I am using a Pic18F45K40 to control an ST7590 power line networking chip which requires an 8MHz clock signal to function. I read the datasheet and it looks like a 16MHz signal can be generated from ...
0
votes
1answer
164 views

Overshoot and undershoot on clock signal

I have created a 50% duty cycle, 8 MHz clock signal on the ATmega32, 0V to 1V. What I see when measuring this clock signal with the oscilloscope is overshoot and undershoot of about +0.2V on both ...
0
votes
1answer
75 views

I2S Clock in Audio Codec on dev board, how is this working?

I'm using a dev board, the keil mcb4300. In the schematic, the audio codec UDA1380HN has the BCKI going to the SYSCLOCK. According to the codec data sheet: BCKI: bit clock input SYSCLOCK: system ...
4
votes
3answers
115 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
0
votes
3answers
98 views

Positive Level Shift a Clock Output using Diode?

I need to level shift a 26mhz 1.8v clock output by .7v on both the high and low side (so clock swings from .7v to 2.5v on output). Would a simple diode/resistor setup like below work for this? ...
1
vote
2answers
94 views

How to set external clock value for STM32F1?

I creating a project with the microcontroller STM32F101C8t. This microcontroller has an internal clock of 36MHz. My question is how to correctly set the external clock value, ie what crystal value ...
2
votes
4answers
164 views

Jitter in 'ppm' and 'ns'

In many datasheets clock tolerance is in ppm and in some other it is in ns or ps. What is the difference in giving clock tolerance in ppm and ns/ps. How it can be converted from one unit to another?
0
votes
1answer
173 views

When a VHDL code with a rising edge clock is synthesized, what happens at the falling edge?

I'm a newbie to VHDL and I'd really be grateful if someone could help me solving this question which has been bugging over the last few days. I don't have a code for this. Assuming, if there's a code ...
2
votes
1answer
42 views

Digital sample and hold synced with a CLK

So I though this should be pretty straightforward, but apparently it's not. Supposed we have a digital async input signal and a CLK. I want to sample the given input signal on every rising (or ...
0
votes
1answer
83 views

How to make sure a clocked operation happens just once in Vhdl

title may be a bit confusing but what I try to do is to take data from ram/modify it and put that data back to the ram. I want all of this to happen just for the operation(Brightness/Contrast) time ...
1
vote
2answers
87 views

Create a pulse that is active from ~0.3 to 0.4 times the clock period

I'm sorry if the phrasing is somewhat weird, but the question is hard to articulate. I've created an IC Sample-and-Hold where I have a hold capacitor at the output. I want to charge this capacitor ...
2
votes
2answers
399 views

Correct terminology for 'clock' that doesn't oscillate?

What would be the correct term for a clock input that isn't made to oscillate per se? In an attempt to only allow input A to have any effect on a circuit at a chosen time, one could AND it with ...
1
vote
1answer
50 views

Is a good practice assigning clk to a signal before component instanciation in FPGAs?

I am working with VHDL for Xilinx FPGAs and I am trying to create some hierarchical components. When instantiating a component B inside another component A, what clk is expected to pass to the ...
0
votes
1answer
67 views

How to connect a 4-pin OSC (crystal oscillator) to an IMU (BNO055) with only 2 pins dedicated to an external clock?

I am using the BNO055 : https://cdn-shop.adafruit.com/datasheets/BST_BNO055_DS000_12.pdf and I can't seem to figure out how to connect a standard external oscillator clock to the chip. As suggested, ...
0
votes
2answers
34 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
1
vote
0answers
44 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
1
vote
2answers
438 views

clock frequency divide by 5 vhdl

i want to get the clock frequency divide by 5, can i do it with integer type or i need something else to run the decimal number? ...
2
votes
2answers
136 views

PCI-E throughput calculation

could someone please do for me the calculation of total throughput of PCI-E? The best material I could find was a Xilinx pdf that mentioned 2.5Gbps as reference value and somewhat awkward formula that ...
12
votes
3answers
3k views

How do processors control their clock speed?

I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power. For something like a desktop processor where the clock ...
0
votes
0answers
19 views

STM32F7 slow systick issue

I am using the stm32f746vgt6 on a custom board v1.1. I just witnessed a strange occurrence that is intermittent and only on one board (so far). The systick interrupt was firing very slow. I'm ...
0
votes
1answer
103 views

Enabling external reference to HP/Agilent Signal Generator (8648C)

What is the proper way to use an external 10 MHz clock signal for an HP/Agilent signal generator (in my case: 8648C)? With my Tektronix, Rohde & Schwarz devices, internal/external reference has ...
2
votes
2answers
123 views

Crystal oscillator on custom ATMega2560 board is at the wrong frequency

I have designed a custom board using an ATMega2560. The board works fine when configured to use the internal oscillator. The board stops working when I configure it to use the the external 16MHz ...
-1
votes
1answer
48 views

Clock impulse through push button [closed]

I need to store 4 bits in a shift register giving input through a push button. For which I also want to generate a clock pulse with the same push button with some delay(<100ms) so that the clock ...
1
vote
2answers
70 views

Can I use a common Clock pin on my micro-controller project instead of separate clock pins?

In my Propeller project, I have the following devices, with the related pins: DS1302 RTC SClk - IO - CE Micro SD Card SClk - CD - CS - DI - DO SPI SRAM x 2 SClk - SO - SI - CE PS2 Mouse ...