Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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Driving a Seiko Slave Clock

I recently acquired a Seiko slave clock, like the ones used on ships. It has 2 coils, one for advance and one for retard. I'm intending on making a master clock for this out of an RPi or ESP32 or ...
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31 views

Master-slave flip flop without gate delay?

It seems like a master-slave flipflop always has around a 2-gate delay between the Master and Slave sections of the flip flop. For example: My question is what would happen if, theoretically, there ...
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How does one get ticks of a clock from an atomic clock's microwave signal?

I understand that in an atomic clock there is a microwave signal that is locked to the frequency of the atomic rotation. However, if one wants to extract time ticks from the microwave signal (shown ...
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44 views

Can you have different clocks working at different intervals to operate a flip flop?

Is it possible to have two clock signals driving a JK toggling flip flop, in which both signals are connected by a XOr gate so that the flip flop only works on either edge of either clock? If possible,...
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33 views

MIC1557 clock frequency constantly increases. Why?

I'm trying to get a 19.2 KHz frequency out of the MIC1557 clock generator. I managed to get close enough (enough for my application) to this frequency with off the shelf components. The shematic is ...
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22 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
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96 views

20MHz clock signal over several PCBs

I am running a 3.3V 20MHz clock signal for LED drivers over 10 PCBs that are connected to each other over short cables. Overall, the clock signal must travel 1m. Is this even possible with a 20MHz ...
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62 views

Is a typical register rising edge or falling edge? [closed]

I'm using Logisim to build a 1-bit CPU. However, I am having issues with timing the registers up with the clock. In a CPU, should registers be rising edge or falling edge? Or, could they be something ...
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23 views

How to pick clock speeds for a CS4270 codec?

I'm in the process of designing a circuit which includes a Cirrus CS4270 codec and a STM32F405 running as a DSP. I'm trying to define my max usable settings, which would be running at Fs = 192kHz. I'...
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83 views

Verilog finite state machine won't reset (asynchronous) current state to initial state (shows xx)

I have mostly worked on VHDL and I have recently started learning Verilog. I wrote a Moore Finite State Machine (FSM). The FSM is not resetting properly as current state upon reset doesn't go into ...
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Equipment and approach for performing a long-term measurement of clock signals

This is a follow up question for the circuit I designed with the inspiration from here. The circuit works but over time there appears to be some clock jitter or skew. I am interested in an approach to ...
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50 views

Unexpected result reading pin on clock rising interrupt

What I try to achieve is a simple one-way communication between two MCU's (ATTiny85's to be exact) at 16Mhz. This is just a start, to figure out it can be useful, very basic and needs to be very basic....
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134 views

How do computers execute instructions spanning multiple clock cycles?

There are some(or most) instructions in a computer that simply cannot be executed in a single clock cycle. But there lies a problem. How does the program counter in the computer know when an ...
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2answers
41 views

Clock Issues from Buffer

I'm testing a board that is having clock issues. The design uses a 40 MHz oscillator, which outputs a clipped sine wave. The clock goes into an inverter buffer to get a 3.3V, 40 MHz sine wave. When ...
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45 views

soc clock domain questions

Those days there have so many different protocols in the soc which basically means different clock rate. In a Soc system, there have CPU which run at some clock speed, then there have memory(dram) to ...
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98 views

Internal oscillator drift and its effect on UART

I am eager to know whether a 150kHz drift of internal oscilator clock (mentioned in a STM32 MCU operating with 8MHz internal clock) could destroy a UART connection?
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53 views

Changing frequency of input clock port (FPGA)

I', using xilinx ultrascale FPGA (xcku025-ffva-1-a) I am referring to application notes provided by xilinx. I am going to use the reference code provided in xapp1315. In this reference code, an ...
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75 views

Produce a clock out (5 MHz) with a counter and a clock in (50 MHz)

I'm trying to solve previous years' tests in logic design and there's this question that I can't really solve.. So, it gives me an 8-bit counter and a clock in (clk_in) of 50 MHz and it asks to ...
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1answer
42 views

Accessing same variables in Verilog on different clocks

I have a 50Mhz master clock clk and from that I have a derived baudClock clock which runs at 9600bps. I have a transmitter module that I want to follow a state machine flow every baudClock. The ...
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72 views

Circuit with two clocks

Most digital circuits can be built in more than one way. However, the easiest way I've seen to build an edge-triggered D flip-flop is with a pair of D latches. One has ...
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4answers
88 views

Digital clock source

I'm currently on an adventure into digital electronics. I've built a bunch of logic, but to test it I need a clock source. Is there a way I can “easily” construct a square-wave oscilator adjustable ...
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1answer
64 views

ATtiny13 at 16MHz? Why not?

How exactly are you supposed to run the ATtiny13 at 16MHz or higher if you really have to? What is the method and what external circuitry do you need to add? Is it altogether more hassle than using ...
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2answers
55 views

Unpowered clock divider

I am not a professional in this area, so I hope I am asking questions correctly. I have a 5V clock pulse with 50-200Hz (square wave) and would like to build a simple unpowered clock divider. Output ...
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1answer
61 views

How do I implement the clock into this testbench?

I am trying to write a testbench for an adder/subtractor but when it compiles the clock does not shift. Here is the verilog for the adder/subtractor: ...
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83 views

Clock divide by 5 - All ICs obsolete?

I've got an obsolete part in a design (SY100S839VZG) that is being used to take a single 100MHz clk and divide it down into two PECL p/n pairs. For the life of me, I cannot seem to find a single ...
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217 views

Circuit for converting 48kHz to 12MHz

I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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83 views

circuit to detect chess clock toggle change to fire BT button

I was looking for simple circuit: (SamGibson's idea to add a 2nd reed switch proved possible, see update below.) to detect transition to flat 0 V when player B's clock is running. to detect ...
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26 views

AT91SAM7S512 Oscillator, GPIO, & Reset questions

I just need some clarification of my circuit Oscillator: So for my circuit I want to be able to program it via USB, the datasheet gets a bit confusing to me tho. If I read the datasheet correctly I ...
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How can I estimate the speed of this code section for this microcontroller?

I'm using an ATmega328P to read the state of a digital input by using the following code section written in C (there can be alternative ways, but this is an example). ...
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1answer
61 views

What circuit will output a short latch pulse when the clock input pauses?

I'm transmitting serial data across a cable to a shift register. I transmit data in discrete packets, where different packets have different bit lengths. The clock frequency is about 20 MHz while ...
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2answers
109 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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1answer
44 views

How to compute clock cycle time from given frequency

let's say I have a processor runs at 100MHZ frequency how can I compute from this it's clock time for each cycle? I know that Frequency = 1 / Clock Time but I am having trouble to fully understand how ...
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1answer
103 views

1 Hz Clock Signal With CD4060 vs CD4521

I am building DIY digital clocks as a school side project. I need to generate a 1 hZ clock signal. I currently have some 32.768kHz crystals but I need to choose an IC. I don’t want to build the ...
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pic16f877a problem in timers with proteus simulation

I used PIC16f877A at proteus to do timer interrupt. The code is pretty simple it has nothing to do rather than setting the timer1 registers , the while(1) loop is ...
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1answer
127 views

Why pick 262144 Hz oscillator frequency?

Some Bulova watches (for example the Precisionist collection) use 262144 Hz crystal oscillators instead of the usual 32768 Hz. What are the true advantages of this higher frequency, if they even exist?...
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210 views

Crystal oscillator using 7404 is unstable

I am currently building a small Z80 microprocessor system and require some kind of clock generation. It is not my first design: Earlier I used an Arduino pin that generated a slow clock or a 555 timer....
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49 views

Novice question about setting system clock in microcontrollers

This is a novice question. I see that for every embdded project system clock is set by using PLL multipliers. But what determines the system clock value? Why not always max system clock is used? Can ...
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49 views

Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous

This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?. I want to use that "register file" for my project, but I need to make it behave properly as a ...
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98 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
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1answer
48 views

Is an unlocked PLL an open-loop clock? And is a locked PLL a closed-loop clock?

What is the difference between an open-loop clock and a closed-loop clock? Is a PLL with an oscillator lock a closed loop clock? Is a PLL without an oscillator lock an open-loop clock?
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195 views

I2C data sampling is done at clock edge or level

I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication. One ...
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Does an ISP clock interfere with the on-board clock when programming via ISP?

I am planning to use ISP programmer to program my new AVR board. I use an 8 MHz crystal on my PCB to clock the micro (atmega328p-au). Now, as I understand the ISP programmer will provide its own clock ...
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Increasing system clock frequency on STM32F303 drops I2C clock proportionately - why?

I'm trying to figure out a weird little issue I've discovered while debugging another element of my code. I've got a STM32F303K8 reading and writing to an I2C peripheral. The I2C clock speed is ...
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1answer
78 views

4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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52 views

Capacitor on clock line of TFT display

Short version (can provide more information if wanted) we have a display (TFT with TTL driver) that we control via PIC32 and Epson Display IC. The supplier changed their driver which should have been ...
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How can I test wether my OCXO VCO is working fine?

I recently bought a PTOC32227 OCXO (datasheet) from eBay (secondhand). It is supposed to output a square wave at 10MHz. However, it is a part of a bigger circuit that is not working properly and it ...
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How to communicate faster than the system clock

I was reading about the new (ish) Thunderbolt 3 today, and was very impressed by the specced speed of 40Gbps. Then I looked at Intel's latest i9 processor speed... about 4.2GHz max. How can a system ...
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1 kHz clock over long wire

I will have a wire that will run up to 1000 m with many nodes connected to it. The wire will run along a CAN bus and a ground wire and must transport a 1 kHz square wave 50% duty-cycle clock signal to ...
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78 views

Mystery bug while programming Atmel micro

I'm programming an ATSAME51J20 micro on a custom board with a J-link Plus compact programmer using the SWD protocol. It is successful for small programs, but fails more frequently for larger programs. ...
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What's wrong with my timing diagram?

I have made this simple timing diagram that presents the triggering way of D flip flop. The flip flop is triggered by clock's rising edges. I am convinced that the diagram is correct signal-wise. ...

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