Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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4answers
44 views

Hold time of a D Flip Flop

which is the physical cause of hold time of a D flip flop? Why is it necessary to keep its input data constant for a certain amount of time?
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19 views

Multi-cycle operations within Logisim [on hold]

I'm working on a circuit within Logisim. I have a FSM and a set of Registers the register in the diagram is a Parallel Access Shift Register and my question isn't in regards to the FSM itself, my ...
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1answer
47 views

Common clock signal to several components over long PCB lines

How to drive a clock signal to 20 digital microphone. The clock is generated from FPGA and about 3MHz frequency. First mic's line 2cm and last one's 15cm away from FPGA clock out pin. Also all mics ...
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2answers
85 views

Compensating clock drift “by hand” - what have I solved?

Edit: I'm not actually looking for a solution, because short of syncing the hardware clocks (which I can't do) there isn't one. What I'm looking for is an explanation of where the magic -8.4ms I seem ...
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1answer
64 views

Clock failure detection on FPGA

So I'm designing an FPGA based device, it has two clock sources, one is 48 and other is 64 MHz and I need to implement a detector if one of them (or both) is not present and light a warning LED. How ...
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2answers
57 views

Digital Alarm Clock in Multisim. (Home Work/ Final)

I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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1answer
43 views

Voltage clamping for nixie tube driver

I want to design a nixie clock based on a high voltage shift register: the HV5530. I don't what to multiplex the tubes to avoid loss in brightness. My idea is to leave the anodes powered all the time ...
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0answers
40 views

Choosing clock buffering circuit

The modular 5V-powered design's module is having two output clocks (21 MHz and 3.5 MHz) to other modules in the system. I am looking for the best way for buffering these signals so that they would be ...
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1answer
100 views

why pre-post amble is required?

why do we need pre-post amble for READ or WRITE DQS ? 1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
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1answer
32 views

Acceptable designing two clock generators using single package?

The circuit I usually use is Pierce oscillator: (pic source) I have always had single system clock in the system, built on single HCU04 chip. Now I need two: 6*NTSC and 4*PAL - frequencies not ...
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2answers
780 views

Does this circuit have marginal voltage level problem?

As a research for the problem I described here I found this circuit by Maxim: This is clock doubler, and must be a really good fit in my case as input frequency is very well defined. However looking ...
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1answer
71 views

Video clocking: crystal or generator?

The video processor (VDP) has 6*Fsc (21,47727 MHz) clock inputs, pins XTAL1 and XTAL2, which is inversion of XTAL1. Present circuit is built using quartz oscillator of above mentioned frequency, and ...
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1answer
84 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
51 views

External CLK in Artix-7

I try to design a board with an ARTIX-7 FPGA. There is a big question that which pin of FPGA should I put an oscillator? I inspected a document about clocking the 7 series xilinx FPGA (7 Series FPGAs ...
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0answers
42 views

CLK signal on DAT0 line on SD protocol?

I'm facing some problems in the initialization stage of the SD protocol on a custom board, specifically when sending the ACMD51 command and reading the Status Card ...
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2answers
56 views

Implications of dynamic frequency scaling in an embedded system

Dynamic frequency scaling is used to increase or decrease the speed of a processor to conserve power, heat, etc. I've seen my own processor fluctuate between 3GHz and 3.5GHz. What are the ...
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2answers
44 views

Impedance matching 2MHz clock 2m cable PCB to PCB

I am starting to design one of my first instances where I think impedance matching/ reflections might be an issue. I want to daisy chain a clock from four seperate PCBs with a distance between PCBs ...
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1answer
34 views

RCC clock freq in STM32F103

If I select internal clock source to run my TIM3 in TM32F103 (TIMxCLK from RCC) as shown in the attached picture: CK_INT Then how to find out what is the freq of this clock? I am using External ...
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1answer
60 views

Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why ...
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1answer
37 views

Relationships between instruction execution and clock cycle in modern CPUs

I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as ...
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3answers
98 views

Is it possible to get complementary clock output from a clock generator such as a 555 timer using simple digital logic?

I'd like to get complementary output from a 555 timer. I've seen previous suggestions of using a D Flip Flop, which is a fine suggestion, however that halves the frequency at the outputs of the flip ...
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1answer
31 views

TLC5926IPWPR Clock width

I'm using the TLC5926IPWPR in a design. It uses an SPI interface. The TLC5926IPWPR chip is on a separate PCB than the MCU that is controlling it. The Clock and SDO pin must go through a cable about a ...
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1answer
2k views

Why does this rising edge detector using a capacitor and a resistor work?

So in this video from Ben Eater he makes a rising edge detector using a capacitor and a resistor like the one below. simulate this circuit – Schematic created using CircuitLab In the video Ben ...
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1answer
31 views

Pulse train profile generator for stepper drive step/dir input

All, I am trying to create a circuit to control a stepper drive step/dir input. I'd like to generate pulses starting at 1kHz and ramp up to a 10kHz peak, then decelerate to 1kHz until motion is ...
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0answers
113 views

Frequency divider in Verilog

I am trying to implement a clock divider with a 2^8 bit different frequencies. I understand that i need a counter that will count and once it elapses change some variable state and based on that ...
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60 views

How to get a low clocking rate by ARTY 7?

I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture ! What are the other choices I have ...
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3answers
109 views

Is there a low voltage LED alternative?

I am trying to create a tiny little watch that is supposed to run off a coin cell (because it is so tiny) and basically just a microcontroller with a 30ppm 1Mhz oscillator that counts upwards. The ...
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3answers
166 views

What's wrong with my interpretation of what should happen in the circuit and what's happening? [closed]

Here is what I expected to happen: A B C D 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 0 ... Initially, suppose all flip flops have output 0. Then, Q' of the ...
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4answers
2k views

Why is this clock signal connected to a capacitor to gnd?

I am trying to understand the following circuit: My problem is to understand why the CLK signal is connected to the capacitor (C7). The bottom side of C7 is connected with a resistor to GND. This ...
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39 views

PIC I2C clock related problem

I am trying to make an I2C communication with a device by using PIC18F26K83. I use 8 MHz MCU clock. While trying to set I2C clock these options: Use 8 MHz MCU clock & HFINTOSC for I2CxCLK ...
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3answers
98 views

Build a nearly 50% duty cycle, adjustable oscillator using D-FF

Starting from an example circuit, I'd like to simulate and physically realize a D-FF circuit that generates a 50% duty-cycle clock. Scope of this: Clock generator for a test circuit Out 0-5v I don'...
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46 views

Strange CLK-similar signal

I'm reverse-engineering the data bus inside a projection clock to find out how to drive the projection without the clock. I use PulseView with a logic analyzer. What I (think to) know so far: It ...
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1answer
53 views

Full Adder driven by clock [FPGA/VHDL]

I've got Ripple Carry adder (26bit) made from scratch. ...
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5answers
4k views

Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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4answers
572 views

Resetting two CD4017 counters simultaneously, only one resets

I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a ...
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0answers
26 views

Can I use a single clock line for 6 parallel addressable rgb data lines?

I am making a PCB with the dimensions of about 60 (height) mm by 320 mm (width). The PCB contains 5 Letters and 1 logo. The idea is to have 6 datelines in parallel. This way I can have different ...
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2answers
114 views

Why Positive-going clock transitions used in certain ICs

Why do certain ICs like 74ALS174 use an inverter so as to make a Positive-going clock transitions occur instead of Negative-going ? Why can't we just save expense of an inverter by removing it and ...
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1answer
66 views

Can I bridge output IO's from an FPGA that is driving a clock source to drive longer tracks?

Scenario I have a motherboard and a daughterboard that couple through two headers. The motherboard has a 16x16 array of ultrasound speakers each with their own drivers, that works. I drive them ...
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1answer
139 views

Does this clipped-sine oscillator need a buffer?

I'm considering using an Abracon VCTCXO, the ASVTX-11-121-19.200MHz-T to run an AT89LP428. I'm trying to make sure that they're interoperable, but the Abracon device doesn't say anything about the ...
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1answer
84 views

Clock synchronised to pulse

I'm thinking about 1Mhz clock signal synchronised to external random pulses (eg. rising edge). Before pulse event clock can be running or stopped. After every pulse, it should run in same fixed phase ...
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0answers
106 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
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0answers
21 views

Tracking ADC Control Logic Not Counting down, only up?

I'm working on trying to build a "tracking" type ADC from individual components. Shown below is my schematic using the parts available in Multisim. The design is based on the 74LS191N 4-bit Up/Down ...
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2answers
91 views

STM32F405 Setting Clock Freq Less than Max 168 MHz

For STM32F405 the max system clock frequency is 168 MHz. I want to run it at marginally lower frequency only for the sake of safety and reliability because my application will run non-stop through out ...
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3answers
73 views

Deciding which assembly is more common positive edge detector

I know of two circuits which can act as edge detector: A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
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1answer
53 views

Zero-R Resistor on XTAL pins

Looking at the schematics of the STM32F4-Discovery board page 28, whose screenshot is attached below.. there is a Zero Ohms resistor 'R25' which is shown in the circuit with the Crystal. And there is ...
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1answer
52 views

MASTER Clock output from one micro to another vs independent clock src

I have a Small STM32 Nucleo board where the on-board ST-Link debugger has an 8mhz crystal for the debugging microcontroller. That microcontroller is set up to output its MASTER clock, in other words ...
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0answers
42 views

AES Sub Byte subsitution in four clock cycles

I am trying to implement AES in verilog using 32-bit data path, but I am not able to subsitute the 128-bit in just four clock cycles, my code requires five clock cylces, Here is the small portion of ...
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123 views

STM32CubeMX Timer Clock Source

If i am using External oscillator with STM32F407 and I select 'Internal Clock Source' for a Timer then what would that mean? What clock frequency will the Timer/Counter register see at its input if my ...
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3answers
372 views

555 Clock Circuit - how to choose resistor value? [closed]

I need to design a 555 clock circuit to output a clock pulse of a specific frequency. The circuit I'm using is this one (from here): I've used this circuit before and it works fine but the website ...
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3answers
202 views

Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...