Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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2answers
61 views

How to get a 1 clock period pulse from a constant signal clock input on every 64 clocks?

I would like to "extract" a one period pulse from a constant clock signal on every 64 clocks. This pulse signal is to be used for reset. What kind of logic circuit should I be looking for? ...
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Clock Generation with PWM?

I'm designing a device with a central MCU/MPU and two external peripherals. The MCU has an internal clock frequency of 110 MHz. I'd like to use the MCU to generate separate clock outputs for each of ...
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Why do some microcontrollers have numerous oscillators (and what are their functions)?

Currently I am reading through the Arm based ATSAM4L series datasheet, and in the sections BSCIF and SCIF I have encountered at least 8 different oscillators/clocks (see image below). I understand ...
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Determining jitter for Vivado clocking wizard?

I have an Artix-7 FPGA AC701 board. In the documentation, it says that it has a 2.5V LVDS differential 200 MHz oscillator (model name: SiT9102AI-243N25E200.00000). I went into SiT9102 datasheet and it ...
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1answer
46 views

Why would a CD4060BE produce a copy of an input clock signal?

I am making a CMOS logic clock and I have a problem with the 1Hz signal generator (see schematic below). When I connect up the CD4060BE chip to a crystal the output on Q8 of the second chip does not ...
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1answer
46 views

Reference clock in FM receiver chips (si4735)

The datasheet is mentioning a 32678 Hz "reference clock" (RCLK) input. It appears to be a well known thing in this type of ICs because it's highlighted in the list of features. I guess ...
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1answer
62 views

T_hold and T_setup help me understand?

My exam is tomorrow and there is something I don't understand in the material, so I really hope to get some help with this. Giving the following circuit: And giving that both FF are connected to the ...
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4answers
99 views

Crystal tolerances and what that means for timer interrupts

I'm developing a system that needs to periodically wake up and perform a process. We're currently targeting for an hourly wake up (give or take, this spec is very loose). The key here is the unit cost ...
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4answers
119 views

Problem mapping VHDL onto development board

I have a very frustrating problem and would really appreciate some help. I am trying to test a RAM block using the switches and LED's on board the Nexys A7-100T FPGA development board. My code is ...
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3answers
806 views

How can I avoid a clock glitch?

I have a clock with a 50% duty cycle, driving a 3-bit ripple counter. When Q2 is high, external lines such as address are stable. I want to generate a short read pulse between 50% and 75% of the Q2 ...
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How can I run a 12 volt car clock on C or D batteries?

I have an old vehicle that I use a battery shut-off on so the clock doesn't tell the correct time. I would like to figure out how to run it on alkaline batteries instead. I have no idea how to do that....
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1answer
32 views

SPI Timing of WIZ850io

I can't understand the SPI timing diagram, I had search through various websites for timing diagram but I have no idea how to interpret this timing diagram of WIZ850io. I am currently trying to form a ...
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2answers
149 views

D-Flip-Flop Hold and Setup Timing Requirements

Update: The answer is 28ns for sure Giving the following circuit and timing table: Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is ...
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1answer
83 views

D-Flip-Flop Hold and Setup Timing

I am solving some question to prepare for my exam but got stuck on this one and need your help. Giving the following circuit: Where input x gets updated 10ns after ...
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0answers
42 views

How to set SPI clock speed for MT7623N

first I must say, I am new to the HW programming, but I really enjoy it. My first project is writing a library for MT7623N (BananaPi R2) that handles GPIO pins. I got the GPIO part done and I can set ...
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I need to write a verilog code to generate a signal which goes high for one clock pulse after every tenth clock pulse

I need to write verilog code wherein I need a signal which goes high for one clock pulse after every tenth clock pulse. I tried something this way, ...
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1answer
100 views

Clock domain crossing between OV7670 interface and AXI4-Stream

Update 1: My first approach is to use the xpm_cdc_handshake macro in the following way: ...
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2answers
90 views

FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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2answers
91 views

Maximum data rate that can be achieved between PIC and FPGA

We are looking at PIC24FJ256GA705 here. It is connected to an FPGA and the FPGA must transfer a few kB of data as fast as possible. I assume that parallel transfer is the best option here, parallel ...
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1answer
311 views

Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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2answers
69 views

Capacitor for triggering negative edge J-K Flip Flop's Clock

I have some SN74LS73AN Flip-Flops which, if I understanding well, are triggered by the negative (falling) edge signal of a clock. I wish to use a simple pushbutton as a clock, and I am aware that, for ...
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1answer
29 views

Low impedance complementary negative level shifter for a BBD

I'm trying to clock a BBD (Bucket Brigade Device) circuit (for example the MN3007) from a microcontroller output. However, the circuit requires a complementary negative clock, i.e. CP1 is \$-12V\$ to \...
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51 views

VHDL state machine using different clocks

I have a state machine inside a process. I want to base the process on two different clocks. Is it possible to use clock1 to clock state1 and clock2 to clock state2?
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2answers
83 views

How deos this clock generator work?

This circuit shows a clock generator, where a capacitor is charged to a certain voltage for half a period (phi opening switches S1 and S2). The same voltage but with negative polarity will be shown to ...
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1answer
46 views

How is clock signal edge detection done / pros and cons of different approaches? [closed]

I'm currently learning about flip-flops, and I'm curious about the different ways in which the clock signal is handled. So far I've come across 3 different techniques: AND-ing the clock signal with ...
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1answer
77 views

What exactly are the tradeoffs between terminating a transmission line carrying a digital signal in 50 ohms versus high impedance?

I have a black box that outputs a 1.28 MHz clock signal that I need to buffer and distribute. If that signal is terminated into 50 ohms the voltage is so slow <1.5V it won't register as high for ...
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Impact of reduction on Dynamic energy and dynamic power in microprocessors

A microprocessor has been designed to have a dynamic switch which reduces power consumption when the loading reduces. Assuming a reduction of 20% in voltage reduces clock frequency by 20%. Calculate ...
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0answers
40 views

Clock line of SDIO bus has worse rise/fall time than rest of bus

I have an ATWILC3000 wifi module connected to a Raspberry Pi Compute Module 3+ over 4-bit SDIO. It's throwing a lot of bus errors at higher frequencies (currently running at 1 MHz for stability when ...
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1answer
55 views

Input Voltage LM8560

I am currently building a digital clock using the LM8560. In the datasheet it says the maximum voltage at each Pin should not exceed +0.3V or -15V. The IC uses the line frequency of 50/60Hz, which is ...
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28 views

Logic.ly JK Flip Flop Input Error

I am trying to stimulate a JK Flip Flop in Logic.ly But, when the input is 0 in the circuit shown below, there is an error, which I cannot pinpoint. How do I fix this? This is the initial circuit: ...
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2answers
70 views

Why do we use a low resistors on Data lines for an ADC for example or a clock?

Why do we use a low resistors on Data lines for an ADC for example or a clock ?
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1answer
309 views

Difference between clock cycle, machine cycle and instruction cycle of the CPU

There is a lot of ambiguity between the definition of these three terms. So, I wanted to know what is the intuition behind these terms and how all three are connected to each other.
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1answer
46 views

programmable timer / clock generator

I need to generate a square wave / clock with configurable frequency between say 60 to 500Hz. There are not stringent requirements on the frequency stability. I need to be able to modulate this ...
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1answer
257 views

Understand an I2C clock line implementation

I am trying to understand a C function from a legacy project which is supposed to manage the clock line for an I2C interface. It basically does as follow: Set pin to output: ...
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1answer
104 views

How to create a cycling clock circuit from scratch?

I'm thinking about doing a project where I have basic components (hex inverter chips, breadboards, jumper wires, transistors, capacitors, etc.) and I create a simple computer. I've been trying to ...
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39 views

How can I make this symmetric non-overlapping clock using digital Logic components?

How can I make a (dead-time) non overlapping symmetric clock like this with digital components such as inverters and NAND gates with 7 separate phases? The first photo is doctored to show what I want ...
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1answer
134 views

How to generate 5 MHz clock with 50% duty cycle?

How to generate a 5 MHz clock with 50 percent duty cycle? I have an application that requires a continuous clock signal to operate. 555 timer is an easy option but it generates only up to 1 MHz ...
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1answer
46 views

Clock signal Series Termination

I was reading about the series termination techniques. I have seen many schematics with 33E series termination for clock signal. Can anybody please let me know why 33E is used & what happens if ...
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1answer
32 views

LC tank connected to t flip flop

A t flip flop needs a clock signal to operate correctly. That clock signal will be provided by a LC tank circuit. Can I just connect the CLK pin to one of the nodes of the LC circuit or is it more ...
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1answer
35 views

Si5350 Driven by MEMS oscillator

I'd like to drive an Si5350 with a MEMS oscillator instead of a crystal for environmental robustness purposes. The Si5350 FAQ says that a CMOS input may be used instead of a crystal so long as the ...
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0answers
42 views

GPS PPS Signal Duty Cycle? [duplicate]

just like the title says, I'm trying to figure out the duty cycle of a GPS's Pulse Per Second Signal. This post and accompanying answers seem to indicate something like a 10% duty cycle: GPS PPS ...
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3answers
100 views

Analogue clock position sensing

I want to control an analogue clock movement with a microcontroller. A Lavet motor is used to advance the hands. The issue is detecting where the hands are. I noticed that some radio controlled clocks ...
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1answer
53 views

How to change the clock frequency of a STM32H753ZI

just got a new MCU for testing and having a hard time changing its clock speed to the maximum (480MHz) Using bare metals or directly manipulating the registers as I never liked the HAL interface. What ...
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0answers
60 views

555 timer unstable pulses

I'm using a 555 timer to drive the clock of my circuit. However, even with capacitors from VCC to GND, and from Pin 5 to ground, I'm still getting this "bump" when the timer transitions from ...
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1answer
59 views

Runtime reconfigurable FPGA clock routing

I have a design with multiple inputs and outputs that should have different bit rates, configurable at runtime. Since there are more I/Os than PLLs, I need to share some PLLs, e.g.: port 1: 1 Mbps ...
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2answers
48 views

IO clock pin far from design, reduce propagation delay

My design is deployed around a particular tile in the FPGA, mainly because of a gigabit transceiver that is located there. However one of the clocks needed for the gigabit transceiver has to come from ...
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1answer
52 views

Why do some flip flops have control inputs? In what ways do they differ from the normal inputs such as J and K?

I'm currently studying sequential circuits and came across this question. Can't figute out the answer. Can somebody help?
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3answers
254 views

Using a counter to count how many clock cycles a signal is high using Verilog

I want to use a counter to count how many clock cycles an input signal is high. The issue I am running into is that once the input signal returns back to zero, my counter resets which causes my output ...
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0answers
35 views

SmartFusion 2 Pin Assignments using Libero

I am currently trying to find the schematic or pinout chart for a MicroSemi's SmartFusion 2. I have read all of their reference documents and release notes, but I can't find which pin is wired into ...
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1answer
170 views

Converting a 50MHz clock to 1Hz to blink an LED

My board uses a 50MHz clock which I am trying to convert to 1Hz so that I can blink an LED. The way my code works is it counts up to 25,000,000 and then the divided clock signal switches from 0 to 1. ...

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