Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

Filter by
Sorted by
Tagged with
-1 votes
0 answers
60 views

Ideas to implement a logic circuit

The circuit has 2 inputs, (clock signal and an input from the top). The circuit has 7 outputs, (all outputs are 0's at the beginning). After each cycle one bit of data is flipped from 0 to 1 (start ...
user avatar
4 votes
2 answers
424 views

Generating a 1pps signal with ~0.1ppm accuracy

Firstly I just want to say I have next to 0 electronics knowledge so if I say something dumb I apologize. I am wanting to make a device which outputs a 1 pps square wave signal that is highly accurate ...
user avatar
  • 43
1 vote
1 answer
14 views

Clock out drive strength - Current

In the datasheet of this IC, what is the benefit or purpose of having 12mA and 16mA drive strength for the clock output pins? What is the purpose of having 2 drive strength values for the clock? Is it ...
user avatar
  • 2,212
0 votes
0 answers
37 views

Ethernet Controller - Signals

I was going through the datasheet of this Ethernet controller IC. I see that the pins are different than that of a Normal Ethernet PHY. Usually PHY has Ethernet Tx and Rx signals and has the MII/RMII ...
user avatar
  • 2,212
0 votes
1 answer
36 views

Meaning of Speed and Duplex pin in the IC

In this - Link of the datasheet, can someone tell me what is the meaning/purpose of the DUPLEX Pin and the SPEED pin. Unable to understand what it actually does and what does it indicate?
user avatar
  • 2,212
-1 votes
0 answers
34 views

Meaning of Virtual PHY, Managed Ethernet [closed]

Can someone tell me what is the meaning of "Virtual PHY", "Managed Ethernet Switch" & "switch fabric". Unable to get a good clarity on what terms actually mean in the ...
user avatar
  • 2,212
0 votes
1 answer
37 views

What is support for an end-to-end and peer-to-peer transparent clock?

In the datasheet of LAN9353, the description states that it supports "supports end-to-end and peer-to-peer transparent clocks" Can someone tell me what is the meaning of this?
user avatar
  • 2,212
0 votes
1 answer
87 views

How to create 4-bit asynchronous counter?

I am new to Multimedia Logic and am trying to create a 4-bit asynchronous counter. I did something like this, but it doesn't work. I'm not sure if everything is properly connected and if I was using a ...
user avatar
0 votes
1 answer
67 views

When should we switch from an internal FPGA oscillator to an external one?

I'm about to design a 5Mbps UART on a ICE40U0-5k and I've got a hunch I'll need an external oscillator when I spin my own board after I'm done with the dev board, but I would like to know how I can ...
user avatar
  • 1,080
0 votes
2 answers
63 views

Do I need RTC while I'm using NTP?

We know computer and another device like microcontroller is not accurate in ticking clock comparing to wall clock that using cesium atom. I heard RTC module is purpose to making accurate the ticking. ...
user avatar
0 votes
1 answer
87 views

How to fill flip flop clock truth table? [closed]

I have this truth table that I want to fill, however, I have no idea how to read the flip-flops on the left. Can anyone provide me a minimal example of how to approach this problem? EDIT: drawing ...
user avatar
  • 137
1 vote
0 answers
71 views

How to calculate the output impedance of an oscillator?

Is it possible to approximately calculate the output impedance of an oscillator if the rise/fall times at a given load capacitance are known, simply by using the formula for the RC time constant T = R ...
user avatar
1 vote
2 answers
64 views

Running a 220V siren with a digital clock

I'm trying to run a 220V siren from a digital clock that, upon reaching the set time, outputs 7.5V for about 2 seconds then stops. Now, I don't understand much about relays, but I did a little ...
user avatar
  • 11
0 votes
1 answer
65 views

Media Independent Interface

I'm reading about the PHY, MAC and the MII interface. I understand that the MDI interface from the RJ-45 to PHY will be 10Mbps, 100Mbps or even higher to 1Gbps. But when this data signals move to the ...
user avatar
  • 2,212
0 votes
0 answers
36 views

Clock diagram schematic symbol [duplicate]

I am not familiar with the schematic symbols outlined in the above digital clock diagram. I gather it indicates an on / off switching connection of crystals "EXTAL" and / or "XTAL" ...
user avatar
  • 387
0 votes
0 answers
41 views

Slew Rate/Rise time conversion

I just wanted to confirm that my oscillator will drive my circuit correctly. I am focused on rise time vs slew rate in this calculation. The receiver which runs off 1.8V has a slew rate of 1V/ns which ...
user avatar
  • 111
1 vote
1 answer
49 views

EEPROM usage in ZS-042

I have bought a realtime clock module (this one). According to the sparse data I found there is a EEPROM on it. It's called 24C32 as can be seen on this schematic I found: As I want to rebuild this ...
user avatar
1 vote
3 answers
77 views

Making 2 clocks with phase shift

I'm trying to create 2 clocks with phase shift for 1/4 cycle time: ...
user avatar
  • 13
0 votes
2 answers
100 views

Checking the signal frequency in FPGA

in a VHDL project where the master clock is 50 MHz, how to check if a signal is 10 MHz or 20 MHz? I have an external device where the default is 10 MHz. I am adjusting its settings via serial port and ...
user avatar
  • 121
1 vote
1 answer
61 views

Switching transistor for micro solenoid

You may have seen some previous posts of mine asking various questions about frequency dividers. I have a circuit I think I am happy with for producing at 1Hz 12.5-25% duty cycle. I now would like to ...
user avatar
0 votes
0 answers
32 views

Reading sensor data - help with timing chart

I am reading data from a C12880MA mini-spectrometer from Hamamatsu, I am having a bear of a time understanding their data sheet. I am able to read the data from the spectrometer, however I want to ...
user avatar
  • 11
0 votes
2 answers
79 views

How to use 74LV8154 to divide 32 kHz clock input

I am trying to divide a 32768 Hz clock input down to 1 Hz using only one chip because space is a concern. I was recommended to use a 74LV8154 from TI but I cannot find any examples of how to implement ...
user avatar
0 votes
2 answers
123 views

Frequency division ICs

I am working on a watch circuit that I would like to be more accurate than normal. I am using a 32768 Hz temperature-compensated crystal oscillator. I intend to cut that down to 1 Hz with D-type flip ...
user avatar
0 votes
1 answer
53 views

SiT1566 XTAL Wiring

I am looking to use this temperature compensated 32kHz crystal oscillator as the heartbeat of a quartz movement wristwatch. I want the superior accuracy and stability over any other oscillators, and ...
user avatar
0 votes
3 answers
108 views

Simple Clock Division

I am working on a clock project that will use a 32768 Hz temperature compensated crystal oscillator chip, likely a DS3231. I plan to bring that frequency down to 1 Hz using flipflop frequency division ...
user avatar
0 votes
1 answer
69 views

Clock recovery circuit in 100base-t / 1000base-t

I'm trying to understand the ethernet interface. My understanding is that Ethernet is an asynchronous interface since there is no explicit clock signal transmitted along with data. So, when there is ...
user avatar
  • 2,212
0 votes
1 answer
43 views

Clock data recovery waveform

I've read that a CDR block recovers clock from the data stream. Clock Data Recovery Can someone show me a waveform on how its done? Like the carrier wave and modulation wave in FM and AM techniques, ...
user avatar
  • 2,212
0 votes
2 answers
73 views

Is HSE clock is a type of internal clock or ETR?

In STM32 microcontrollers there is a distinction between HSI and HSE(high speed external). This indicates an internal external distinction. On the other hand as shown in this document there is ...
user avatar
  • 1,213
0 votes
1 answer
56 views

LHT00SU1 logic analyzer clock generator

I was using a LHT00SU1 logic analyzer and according to this it should have the capability to produce a variable frequency signal (i assume through the CLK pin). Using pulseview with fx2lafw firmware I ...
user avatar
  • 105
2 votes
2 answers
60 views

What is my DAC clocking frequency for this STM32 board?

I'm trying to figure out the exact clocking frequency of the DACs for this board. Here is the clock config: And the code section for the DAC initilaztion: ...
user avatar
  • 1,213
0 votes
1 answer
102 views

What is the easiest way to generate a clock signal?

I'm pretty much a beginner with electronics, and I am currently making an audio circuit, using the TI PCM1755 24-bit DAC. For my application, the IC needs a 49152 kHz clock to its SCK pin. Is there a ...
user avatar
  • 21
0 votes
2 answers
114 views

Crystal oscillators vs LC circuits [closed]

I have 3 questions about crystal oscillators, their relation with an RF coil and their usage in electric circuits. This image of a crystal oscillator is all over google and youtube, but no one ...
user avatar
  • 235
0 votes
1 answer
61 views

How to store bits asynchronously without clock resetting all bits?

I am working on a circuit that has 8 buttons that need to hold the value once pressed. I'm currently using a 8 bit flip flop (74LS273 in the diagram). The problem is that all bits get reset on the ...
user avatar
  • 3
0 votes
1 answer
49 views

Synchronizing a clock enable signal with an input clock

I'm designing a basic PCB for testing equipment in lab. The goal is to take a clock input, a clock enable (from a PC indicating that the measurement is beginning), and then distribute it to a number ...
user avatar
  • 10.4k
0 votes
0 answers
103 views

How do I change and verify the clock frequency of Atmega4809 microcontroller? CLKOUT not working?

In the below code I am trying to get the clock frequency to show up on the CLKOUT pin which should be pinA7. But for some reason I don't get anything when measuring pinA7 on an oscillicope. I do see ...
user avatar
  • 187
2 votes
1 answer
158 views

STM32 : set APB1 and APB2 to same clock frequency

When configuring a STM32 (or at least my STM32F722ZE based nucleo board), there are 2 clock frequencies, one for APB1, the other for APB2. The annoying thing is that some timers use APB1, other use ...
user avatar
  • 2,573
0 votes
2 answers
61 views

Trying to drive the clock pulse of a counter by a NAND gate output but the counter misbehaves

I have connected the output (2Y) of the NAND gate to the clock pulse (CP0) input of the counter, but as soon as I send an input to the NAND gate the counter misbehaves; it does not count in sequence ...
user avatar
0 votes
1 answer
93 views

Switching crystals circuit

This is for NES clock circuit. I need to find a way to switch the crystal between PAL and NTSC. I have used a normal switch to switch those with no problem. Same goes obviously with a relay, but I'm ...
user avatar
4 votes
3 answers
340 views

Spartan-6 -- Map failed due to using a non-clock pin for a global buffer instance

I'm trying to use Spartan 6 (TQG144) PLL to generate a high speed clock. I used IP core generator to config the PLL. Here is the simple VHDL code I have to use the generated component: ...
user avatar
  • 153
5 votes
5 answers
3k views

What happens if clock cycle is replaced with constant high voltage in a processor?

Would the data in registers change at light speed and maybe become unstable/undefined, or would the processor stop changing state altogether? This post says: To give all the gates time to change ...
user avatar
  • 235
1 vote
0 answers
39 views

PLL Clock distribution

I am generating 40MHz clock using ADF4106 PLL Frequency Synthesizer with VCO CVCO55CL-0038-0042. I am using this 40MHz generated frequency for distribution using ADCLK846. Output power from PLL is -3....
user avatar
0 votes
3 answers
69 views

Phase noise and RMS jitter scaling with frequency

The phase noise plot for a particular crystal oscillator is here. The datasheet represents an entire series of oscillators which range in frequency from 1 to 75MHz. The phase noise plot is indicated ...
user avatar
  • 229
0 votes
2 answers
157 views

Digital Clock Manager FPGA

I want to maintain a constant frequency of 50MHz for my Nexys A7 FPGA Board. Currently, the internal clock is 100MHz. How can I implement a digital clock manager in VHDL/Verilog to make sure my ...
user avatar
  • 11
-1 votes
2 answers
131 views

What can negatively impact a motherboard's / CPU's clock generator / oscillator?

Is it possible for a clock generator / oscillator to be skewed by something from the electrical grid (e.g. to work perfectly fine at place A, and have issues at place B - all reproducible)? What would ...
user avatar
8 votes
5 answers
1k views

What frequency stability crystal do we need?

We're designing a simple digital clock and using a 32.768 kHz crystal with a frequency stability of 20 ppm (standard off-the-shelf SMT). We're finding the clock is running fast by about 2.5 minutes ...
user avatar
  • 81
0 votes
1 answer
49 views

How to trace and find the clock of a certain USART for this board?

I'm having trouble to trace and find which clocks clock USART2 and USART3 ect for a uC board. I looked at clock tree and block diagram of the board but cannot find a hint. I checked both the reference ...
user avatar
  • 1,213
2 votes
1 answer
55 views

MCP2510 CAN controller: 16MHz Crystal not oscillating or oscillating at 150KHz

Issue: I have a board which uses a MCP2510 CAN controller and ATMega 32U4. During testing I found I couldn't communicate with the CAN controller. After some probing I found the CAN controller clock ...
user avatar
  • 31
0 votes
1 answer
101 views

What is IOSTANDARD in ucf file

I am learning FPGA programming. Going through example code/project. What is IOSTANDARD in constraints file. When to use LVCMOS33, LVCMOS25, LVDS_25. Which one is best for high speed clock signals. ...
user avatar
0 votes
3 answers
149 views

In which clock edge does the I2C slave write?

I'm trying to implement an I2C master - slave example in an FPGA (Verilog). As the I2C protocol specifies, the master must make sure that it writes the next bit enough time before the clock signal ...
user avatar
  • 923
1 vote
1 answer
63 views

Clock source of an STM32G030K6T6

I am currently designing a GPS tracker and have decided to go with an STM, choosing just STM32G030K6T6 (datasheet). I currently have the following pinout configured: My question is, since there is no ...
user avatar
  • 125

1
2 3 4 5
22