Questions tagged [clock]
A digital signal that goes high and low at a specific frequency.
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FTDI SPI has short pauses between bytes. Is this expected? [closed]
I am using an FT4232H module for an SPI communication.
Even if I am using the MPSSE engine, and ft_write command sending many bytes together, what I see is a clock ...
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Is plastic package for oscillator bad for EMC?
I usually use oscillators with metal/ceramic package, but I am inherited with a design that uses plastic package. Now it failed radiated emission that aligns with its harmonics. I understand many ...
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How to write tests for a clock signal
I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests ...
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6502 Extra Cycles on Page Cross
On the 6502 processor, when using the Absolute,X, Absolute,Y or (Indirect),Y addressing ...
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I2C data held low and clock held high
We are having issues with the I2C communication on our I2C bus and it seems like one of the INA233s on the bus is causing the issue. We are using the INA233s as current and power monitors. We use ...
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SPI STM32. How to enable clocking of the SCK pin?
SPI configured as Master with software SS.
Which SPI bits do I need to enable to see the clock on the SCK pin?
Image CR1 register.
The image shows that when SS switches to zero, the SCK clock starts ...
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ADC Timing Problems in FPGA design
I am using a Xilinx Kintex UltraScale FPGA (AXKU040 development board) and an ADC board (FL9616 board). I would like to have a design that provides the ADC data as a data stream inside the FPGA. The ...
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Why CPU DDR Memory Controller Has 2 Clock Outputs?
I'm trying to understand the ddr structure for the iMX6 Rex Module .
The cpu used is the MCIMX6Q5EYM10AC model from the NXP i.mx quad series.
MCIMX6Q5EYM10AC Datasheet
iMX6 Rex Module Shematics
A ...
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Expected Outcome of a LVDS Transmitter Output if there's no Termination Resistor
I know this sounds like a silly question, but what would the expected waveform of a LVDS transmitter that has no termination resistor look like? If the expected output were to be a 20 MHz LVDS clock ...
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Is my circuit correct (Nixie Tube Clock)?
I am making a clock with Nixie tubes IN-12 A and made a circuit. I would like to know if it is correct before making the PCB and 3D case.
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What is the maximum PLL output frequency in the STM32H7A3?
I'm setting up a hyperram, and I want to run it at 200MHz, with the DHQC setting enabled. The peripheral manual on page 874 says:
DHQC must not be set when the prescaler value is 0, as this action ...
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Can I read time data from an RTC (Real-Time Clock) chip without a microprocessor?
I have an HD146818 (Motorola MC146818) integrated circuit, which is a real-time clock. I would like to build a simple clock on it, which will control an 8-segment display. I read the datasheet for ...
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Output load capacitance vs max input load capacitance
I am currently in the process of building a frequency divider circuit. To realize a lower frequency of 3.072 MHz. I use the: ECS-TXO-3225MV-122.8-TR
For frequency division and reduction I use D-...
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SCLK : 50 [MHz] Rising Edge vs 25 [MHz] Dual Edge : Tradeoffs
TI manufacturers two near-identical drivers for matrixed LEDs, LP5890 and TLC6983. I was only able to determine the following ...
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How do I limit a down counter so that it counts from 3 to 0?
I've been studying binary counters and learned how to build an up counter that starts at 0 and counts to a set value before resetting. Now, I need to learn how to build a down counter that starts at a ...
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FPGA and SDRAM noise impact on ADC input
I'm using an FPGA to get data from an ADC and save them on SDRAM, the SDRAM works with 100 MHz and the ADC works with a 40 MHz clock so I use a clock IPCORE to generate them from my 50 MHz oscillator ...
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How to get a 60 Hz frequency at Logisim? [closed]
I'm projecting a circuit at Logisim that needs a 60 Hz frequency for the clock. Looking at the Simulate tab it does not show anything like this. I even looked at the documentation, but found nothing.
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SD Card CLK stops working properly on STM32F4 with SDIO connections
I have an SD Card socket connected to STM32F4 with the connections as follows:
The firmware uses the following codes to initialize the SDIO:
...
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I2C VS SPI comunication
I have studied the I2C and SPI communication protocols, but one thing has been confusing for me. In the case of the SPI we have shift registers at both ends and with the help of the SPI rising clock ...
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Why does increasing the period of a signal compensate for clock skew?
My textbook gives the following circuit:
simulate this circuit – Schematic created using CircuitLab
Where both registers are positive-edge triggered D-Type flip-flops.
It describes a how a race ...
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How does setup and hold time affect the minimum clock period?
Do setup time and hold time of a register directly affect the minimum clock signal?
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How different clock signals can be made
I am not a electronics student. While using shift resistor to save data we need to give it a signal such as 1101 which we need to store in it 1101 signal is synchronous to clock pulse 101010. I want ...
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Reliability issues with si5351 when generating two clocks with a phase difference of 90 degree
I am trying to generate two clocks of X-MHz each, X being a value ranging from 5 to 100. I chose si5351 chip for this as a breakout board was easily available from Adafruit. I used attached code to ...
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How does a processor know the amount of time it should hold the address on the address lines
How does a CPU know how much time it keeps the address on the address line or even data because considering the CPU relies on clock to sync its operations.
I've seen the datasheet of the 6502 ...
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Testing an IC : IO PAD experiences 2nd-order ramping effect
The IO is a regular PMOS-PULL-up and NMOS-PULL-dn IO with series resistors on pull-up and pull-dn branches. The IO is input an clock signal around 50MHz and it experiences an approximately 2nd-order ...
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How to make a quartz clock that does not stop
We are an association of French students learning electronics. I'm actually making a circuit to make a quartz clock, I'm looking over the schematic that I found on the net, but I really don't know why ...
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What can cause clock line to have EMI emmisions?
I am trying to understand the topic of EM radiation and EM absorption of PCB clock signal. I think the clock signal is given more important than others since it is toggling all the time.
So since a ...
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Multi-master Bus Systems, Arbitration and Synchronization
I am slightly confused in the multi master system of Atmega328p. I have understood that first the clock is synchronized by taking the logic and gate of all. Then the data is synchronized and one ...
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Creating a large number of crystal-stabilized pulse waves at precise frequencies
I intend to generate 22 separate 50% duty cycle pulse or square waves. The frequencies range from about 5 Hz to 350000 Hz and are all irrational numbers, so I would like as much precision as possible.
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Bandwidth of a DAC
Could anybody specify what does this bandwidth means in DAC PWM?
Source: Designing high-performance PWM DACs for field transmitters (page 2)
The bandwidth of a DAC?
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Calculating AC-Coupled input current
I'm using an SDR which uses and ADF4002-based PLL with its REFIN input AC-coupled via a 0.1 uF capacitor to an external input. I'd like to connect an external reference clock to it, but I'm unsure how ...
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AC 250V 50Hz or 48V DC and reduce the input voltage down to 24V / 1W Output. How can I generate DC/DC converter clock signal
I have to design a a power supply that can accept either 250V 50Hz AC or 48V DC from the same input terminals. Output has to be 5V/1W. Circuit cost has to be below 10 euros. It is meant to work either ...
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Measuring oscillator stability vs temperature
How do people measure frequency stability vs temperature? Is it by having the data of frequency vs temperature and then try to fit the curve and finding the temperature coefficient or by finding ((d(...
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STM32WL55JC1 sampling rate is different
I am using STM32Wl55JC1. STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit (Arm® Cortex®-M4/M0+ at 48 MHz). I am trying to do tone calculator. I am using DSP, ADC, DMA and timer for ...
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SN74HC595 shift registers, cascade connection, SRCLK and RCLK pins shirted
I'm working on project, where we have sn74hc595 shift registers included. Because I got this project without any documentation, it was necessary to understand this connection of shift registers, so I ...
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Is it possible for one oscillator to drive two ICs?
I have this oscillator IC with which I plan to drive a KSZ8795 and an LAN9500A without clock buffer.
The TG2016 output load drive is 10pF for the capacitor.
The KSZ8795 can have a crystal load ...
user220456
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Maintain accurate timing on 1pps 'heartbeat' signal
I have an application where I need to provide a 1 pulse per second 'heartbeat' signal with a very good accuracy over an extended period of time (1 second between pulse edges ± approx. 200 μs for ...
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Setting external clock in ATmega16A
I am confused about how to configure an ATmega16A microcontroller to use an external clock instead of the internal one. I do not know whether I should set up the last bit as 0 or 1 for CKSEL in ...
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Choosing an Appropriate ADC Clock Source
I'm currently in the process of changing the clock source for our scanning ADC (ADS1158) from an internal oscillator with external crystal to an external clock.The datasheet doesn't really give much ...
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Running multiple ICs with a single crystal
I need to run three AD7779 ADCs using the same clock signal for synchronization. I don't have access to an oscillator which I can use as a master clock, so I was wondering how I could use a single ...
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Sharing clock pulse between different devices
I have an application where i want to use the external clock signal (around 1kHz) with my microcontroller. I am interested in positive edge of the clock which will be detected by microcontroller. I ...
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Should clock signals be pipelined across super logic regions?
I am deploying an FPGA design that will take up resources across 3 separate super logic regions (SLRs). However, I've it is having trouble passing timing. The reports from Vivado show that the clock ...
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DAC DDR Interface with Vivado and Zynq7000
i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling ...
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Can AC Coupled LVDS be used in a multidrop architecture
I am designing a system with a clock distribution IC with AC-LVDS outputs.
I would like to connect this into a multi-drop LVDS system. All LVDS receivers will be operating off the same voltage levels.
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What is the role of master clock speed on DAC?
In the I2S protocol we have 3 signal + one none-standard master clock (mentioned by Olin Lathrop):
data
LRCK/FCK (frame synchronizer)
BCK (bit clock)
MCK/SCK (master clock)
Question 1: Why do we ...
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How are status signals such as ALE set?
I am currently learning about the 8085 Microprocessor as a part of my coursework. When I was studying about Timing Diagrams, I got a doubt that, how are these status signals such as \$ALE\$, \$\...
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Clock Fanout Buffer Circuit
I need a clock fanout buffer to drive 3 components with same clock, and I have found this reference design but could not understand the reason of using the inverter in the middle.
Can I directly ...
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translating LVDS to LVTTL using amplifier and high speed output buffer
I am receiving an LVDS clock differential signals and need to convert them to LVTTL .
the problem is that the LVDS frequency is above 500Mhz and the LVTTL output needs to drive a 50ohm resistors, when ...
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LVPECL output circuit explanation
I don't understand the circuit itself, how we will get VOH and VOL on the outputs. There is 2 modes one mode is when Q1 is conducting and the other mode is when Q2 is conducting , how from here how ...
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RC circuit oscillator [closed]
I want to make a simple RC oscillator circuit that produces waveforms of
How can I do so?
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