Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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2answers
53 views

I2C data sampling is done at clock edge or level

I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication. One ...
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Does an ISP clock interfere with the on-board clock when programming via ISP?

I am planning to use ISP programmer to program my new AVR board. I use an 8 MHz crystal on my PCB to clock the micro (atmega328p-au). Now, as I understand the ISP programmer will provide its own clock ...
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Increasing system clock frequency on STM32F303 drops I2C clock proportionately - why?

I'm trying to figure out a weird little issue I've discovered while debugging another element of my code. I've got a STM32F303K8 reading and writing to an I2C peripheral. The I2C clock speed is ...
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1answer
32 views

4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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Capacitor on clock line of TFT display

Short version (can provide more information if wanted) we have a display (TFT with TTL driver) that we control via PIC32 and Epson Display IC. The supplier changed their driver which should have been ...
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How can I test wether my OCXO VCO is working fine?

I recently bought a PTOC32227 OCXO (datasheet) from eBay (secondhand). It is supposed to output a square wave at 10MHz. However, it is a part of a bigger circuit that is not working properly and it ...
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4answers
3k views

How to communicate faster than the system clock

I was reading about the new (ish) Thunderbolt 3 today, and was very impressed by the specced speed of 40Gbps. Then I looked at Intel's latest i9 processor speed... about 4.2GHz max. How can a system ...
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6answers
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1 kHz clock over long wire

I will have a wire that will run up to 1000 m with many nodes connected to it. The wire will run along a CAN bus and a ground wire and must transport a 1 kHz square wave 50% duty-cycle clock signal to ...
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1answer
72 views

Mystery bug while programming Atmel micro

I'm programming an ATSAME51J20 micro on a custom board with a J-link Plus compact programmer using the SWD protocol. It is successful for small programs, but fails more frequently for larger programs. ...
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1answer
63 views

What's wrong with my timing diagram?

I have made this simple timing diagram that presents the triggering way of D flip flop. The flip flop is triggered by clock's rising edges. I am convinced that the diagram is correct signal-wise. ...
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1answer
33 views

Ethernet PHY clock and sync

I have a general question about reference clocks for ethernet PHYs. The PHYs I have seen so far require an external clock source like a xtal or other singleended clock (in addition to the clk lines ...
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1answer
12 views

Logisim Flashing button

How can i create a button with a clock that is connected to a LED that the LED turns on when the button is pressed but even if you keep holding it it will turn off
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comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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51 views

Rising edge detector behavior

I was looking at this StackExchange question: Why does this rising edge detector using a capacitor and a resistor work? I ran the simulation and I'm confused by the behavior. On the rising edge of ...
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1answer
45 views

Clock Multiplier / Clock Boosting

I was reading this paper "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter" by Cho and Gray from 1995. https://ieeexplore.ieee.org/document/364429 In it, they describe a clock multiplier circuit ...
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Programming an ATmega644 with 32.768 kHz external clock and USBTinyISP

I accidentally changed the fuse bits on my ATmega644PA chip so that it is expecting a 32.768 kHz signal in the XTAL1/XTAL2 inputs. I am using the a USBTiny programmer (the Sparkfun AVR Pocket ...
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2answers
64 views

Delay a clock to give time for the input to settle?

I have a numerical keypad that I want to feed into a shift register to display the last three numbers I have pushed. My numeric keypad has ten lines, each of which connects to a common on a button ...
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1answer
59 views

Why a potential divider at high speed LVDS clock outputs?

I recently came across a Xilinx SOC design in which the system clock which is configurable up to sub GHz, being an LVDS clock the output is been divided using a 1.2V rail, as shown below. Will this ...
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153 views

Determining which pulse came first on an FPGA

I try to determine which of two asynchronous pulses came first (after a synchronous reset) using an FPGA. The pulses are asynchronous because they are generated from ring oscillators (running on the ...
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2answers
74 views

MEMS Oscillator not running, why?

For the latest iteration of my prototype, I replaced a quartz oscillator with (what I thought would be) a drop-in MEMS replacement: the DSC6013CI2A-033.0000. It is suppling a 33 MHz clock to a TLC5955 ...
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3answers
95 views

Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
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CS5340 does not generate clock signals correctly

I am trying to build a sound input for Raspberry Pi 3B using CS5340-CZZ as an ADC. I am basically using it according to the typical connection diagram in its datasheet, where I have a signal from a ...
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1answer
61 views

How to understand these 8086 bus cycle timing diagrams

Please see the two diagrams below. In the first diagram, each state (T1, T2, ...) seems to begin with the clock low. In the second diagram - with the clock high. If we look at the DR/R' signal - in ...
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1answer
48 views

Curious Behavior In Logisim while trying to mimic a halt instruction

I'm in the process of trying to simulate a halt instruction based on some arbitrary value. My circuit design may not follow best practices as I'm disabling the overall or master clock sign with a ...
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1answer
97 views

Why does my Atmega328 clock seem to be off by a factor of 2?

I have an Atmega328 chip I am trying to debug. I have a sketch that blinks an LED and echoes back things received over the RX/TX pins. I am using the "Import Arduino Sketch" feature in Atmel Studio 7. ...
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51 views

Consequences of leaving unused inputs of clock buffer floating. Alternative: best practice

I'm using a Si53342-B-GM Original datasheet download at silabs for the si5334x-series as a clock buffer. In some cases I only need to distribute a single clock signal and in some of my cases I ...
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6answers
90 views

Hold time of a D Flip Flop

which is the physical cause of hold time of a D flip flop? Why is it necessary to keep its input data constant for a certain amount of time?
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1answer
49 views

Common clock signal to several components over long PCB lines

How to drive a clock signal to 20 digital microphone. The clock is generated from FPGA and about 3MHz frequency. First mic's line 2cm and last one's 15cm away from FPGA clock out pin. Also all mics ...
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92 views

Compensating clock drift “by hand” - what have I solved?

Edit: I'm not actually looking for a solution, because short of syncing the hardware clocks (which I can't do) there isn't one. What I'm looking for is an explanation of where the magic -8.4ms I seem ...
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1answer
80 views

Clock failure detection on FPGA

So I'm designing an FPGA based device, it has two clock sources, one is 48 and other is 64 MHz and I need to implement a detector if one of them (or both) is not present and light a warning LED. How ...
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2answers
108 views

Digital Alarm Clock in Multisim. (Home Work/ Final)

I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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1answer
48 views

Voltage clamping for nixie tube driver

I want to design a nixie clock based on a high voltage shift register: the HV5530. I don't what to multiplex the tubes to avoid loss in brightness. My idea is to leave the anodes powered all the time ...
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54 views

Choosing clock buffering circuit

The modular 5V-powered design's module is having two output clocks (21 MHz and 3.5 MHz) to other modules in the system. I am looking for the best way for buffering these signals so that they would be ...
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1answer
108 views

why pre-post amble is required?

why do we need pre-post amble for READ or WRITE DQS ? 1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
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1answer
35 views

Acceptable designing two clock generators using single package?

The circuit I usually use is Pierce oscillator: (pic source) I have always had single system clock in the system, built on single HCU04 chip. Now I need two: 6*NTSC and 4*PAL - frequencies not ...
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2answers
791 views

Does this circuit have marginal voltage level problem?

As a research for the problem I described here I found this circuit by Maxim: This is clock doubler, and must be a really good fit in my case as input frequency is very well defined. However looking ...
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1answer
75 views

Video clocking: crystal or generator?

The video processor (VDP) has 6*Fsc (21,47727 MHz) clock inputs, pins XTAL1 and XTAL2, which is inversion of XTAL1. Present circuit is built using quartz oscillator of above mentioned frequency, and ...
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1answer
122 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
64 views

External CLK in Artix-7

I try to design a board with an ARTIX-7 FPGA. There is a big question that which pin of FPGA should I put an oscillator? I inspected a document about clocking the 7 series xilinx FPGA (7 Series FPGAs ...
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60 views

CLK signal on DAT0 line on SD protocol?

I'm facing some problems in the initialization stage of the SD protocol on a custom board, specifically when sending the ACMD51 command and reading the Status Card ...
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2answers
59 views

Implications of dynamic frequency scaling in an embedded system

Dynamic frequency scaling is used to increase or decrease the speed of a processor to conserve power, heat, etc. I've seen my own processor fluctuate between 3GHz and 3.5GHz. What are the ...
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2answers
49 views

Impedance matching 2MHz clock 2m cable PCB to PCB

I am starting to design one of my first instances where I think impedance matching/ reflections might be an issue. I want to daisy chain a clock from four seperate PCBs with a distance between PCBs ...
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1answer
65 views

RCC clock freq in STM32F103

If I select internal clock source to run my TIM3 in TM32F103 (TIMxCLK from RCC) as shown in the attached picture: CK_INT Then how to find out what is the freq of this clock? I am using External ...
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1answer
77 views

Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why ...
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1answer
39 views

Relationships between instruction execution and clock cycle in modern CPUs

I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as ...
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3answers
121 views

Is it possible to get complementary clock output from a clock generator such as a 555 timer using simple digital logic?

I'd like to get complementary output from a 555 timer. I've seen previous suggestions of using a D Flip Flop, which is a fine suggestion, however that halves the frequency at the outputs of the flip ...
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1answer
33 views

TLC5926IPWPR Clock width

I'm using the TLC5926IPWPR in a design. It uses an SPI interface. The TLC5926IPWPR chip is on a separate PCB than the MCU that is controlling it. The Clock and SDO pin must go through a cable about a ...
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1answer
3k views

Why does this rising edge detector using a capacitor and a resistor work?

So in this video from Ben Eater he makes a rising edge detector using a capacitor and a resistor like the one below. simulate this circuit – Schematic created using CircuitLab In the video Ben ...
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1answer
32 views

Pulse train profile generator for stepper drive step/dir input

All, I am trying to create a circuit to control a stepper drive step/dir input. I'd like to generate pulses starting at 1kHz and ramp up to a 10kHz peak, then decelerate to 1kHz until motion is ...
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152 views

Frequency divider in Verilog

I am trying to implement a clock divider with a 2^8 bit different frequencies. I understand that i need a counter that will count and once it elapses change some variable state and based on that ...