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1answer
36 views

Curious Behavior In Logisim while trying to mimic a halt instruction

I'm in the process of trying to simulate a halt instruction based on some arbitrary value. My circuit design may not follow best practices as I'm disabling the overall or master clock sign with a ...
6
votes
4answers
586 views

Resetting two CD4017 counters simultaneously, only one resets

I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a ...
0
votes
0answers
23 views

Tracking ADC Control Logic Not Counting down, only up?

I'm working on trying to build a "tracking" type ADC from individual components. Shown below is my schematic using the parts available in Multisim. The design is based on the 74LS191N 4-bit Up/Down ...
0
votes
1answer
224 views

Building a 7 Segment clock using mains frequency

As the title says, I want to build a clock using the mains frequency (50Hz). I only want to use digital integrated circuits from the CD4xxx series or something similar. (no microcontroller or do-it-...
1
vote
0answers
753 views

Clock Frequency for 4 digit 7 segment display in VHDL

I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider ...
1
vote
2answers
1k views

Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
0
votes
0answers
37 views

How to connect the counter below to the counter above

I am designing a synchronous DOWN counter that is supposed to count down from 20 to 00. I tried many different ways but the logic combinations I tried are obviously wrong as I am getting very weird ...
-2
votes
1answer
897 views

VHDL Knight Rider

I am newbie in VHDL. In my code, everything seems right but code doesn't work properly. I couldn't find where my fault is. Any solutions? ...
1
vote
1answer
139 views

Dual JK Flip-Flop Toogle Feature

I'm trying to make an 8-bit Display using 4 seven segment displays being driven by a single EEPROM (like in this video). From the video, I used the design of the 555 timer and a dual JK flip-flop to ...
3
votes
3answers
358 views

How to create a counter to display 6 digits using anodes?

I'm trying to write a digital clock on vhdl for an fpga that runs on 100mhz. I can write it on 4 anodes by creating a counter as shown below(count1 = 249999), the digits seem pretty clear. However, ...
2
votes
2answers
1k views

Why is a 15 stage binary counter/divider so cumbersome?

There seem to be many ways to take a 32.768kHz signal and turn it into 1Hz. I can use a CD4060, but still have to add a flip-flop... so 2 "large" chips with excess (potentially) unused functions ...
0
votes
3answers
335 views

74LS90N Is not counting!

So basically Im working on a counter from 0-9 and I have made a simulation and it works completely fine but when I implement it on the breadboard it does not count. I have implemented it more than 4 ...
-1
votes
2answers
346 views

Are 7490N & 74LS190N Same IC's? [closed]

As mentioned above, are 7490N & 74LS190N Same IC's? Im a bit confused about these two. Please tell me their name(s) too.
0
votes
2answers
588 views

Why asynchronous counters can not work at high clock frequencies?

Asynchronous counters can not work at high clock frequencies and cause problems with decoding circuits. What does this mean in terms of timing and operation of the circuit? Why a “re-synchronizing” ...
3
votes
3answers
381 views

Count cycles from oscillator clock to get time

first time on stackexchange, hope I'm in the right place. I am working on a project where I need to timestamp an event (which will be detected from an electrical pulse) down to a few tens of ...
0
votes
2answers
806 views

frequency divider by 42 with 50% duty cycle

I want to design a clock divider by 42 from flip flops. Is there a way to do that while still gets 50% duty cycle?
1
vote
3answers
538 views

Understanding Test Parameters on Datasheet (CL pF)

On Page 7 of the datasheet for M74HC590 It uses a CL (pF) At the bottom of Page 8 is the test circuit which shows where the CL(pF) goes, in regards to a circuit diagram, but I don't understand that ...
0
votes
1answer
117 views

JK flip-flop and sequence network

State diagram of the sequence network S looks like the following for a jk flip-flop: Is this the right truth table for it? ...
0
votes
1answer
441 views

Making a clock cp for counter, using a photodiode

I need to make a device that counts light impulses, basicly a light detector counter, i need help with my counter cp, how to implement a photodiode(can't find phototransistors in the stores) to do ...
1
vote
1answer
475 views

Counting PIC18F46K20 internal clock edges using MPLAB C18?

I am trying to create a countdown timer using the PIC18F46K20 and display the time on the OLED. I have set up TIMER0 to create a delay of 1 second ( T0CON = 0b00000001 ) so the variabe intCLKsecs ...
3
votes
2answers
3k views

Johnson Counter VHDL

I have a problem given to me that states: Design a 4-bit Johnson counter and decoding for all eight states using just four flip-flops and eight gates. Your counter needs not be self-correcting....
2
votes
3answers
652 views

Counter: pulse every 8 clocks

I have a square signal (fixed but can be between 12MHz and up to 48MHz) and I would like to create every 8 clocks a pulse as brief as possible, no more than 1/4 of the period. First, a couple of ...
1
vote
2answers
807 views

How to get 460.8KHz from 1.8432Mhz oscillator using counters?

I need to supply 460.8kHz clock to IC (NCR20C12). However, I can only get 1.8432MHz Oscillator. How can generate clock divided by 4 from it? I have a couple of SN74LS393 counters and want to ask, is ...
1
vote
3answers
7k views

How to reset a 4026 counter IC when it reaches 6 for electronic dice

I'm trying to build a circuit to simulate a dice roll using a 555 in astable as it's heart. The output pulses are counted by a 4026 and then fed into a 4511 BCD to 7 segment decoder. It works ...
0
votes
1answer
814 views

Can someone help check my solution for this timing diagram?

I've been working on some timing diagrams and I keep mixing up the behaviors for the different flip flops. EDIT: I think I have the logic correct. If someone could please let me know if I'm anywhere ...