Questions tagged [clock-recovery]
Questions relating the recovery of timing information in serial communications.
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Designing circuit of clock recovery from data line [duplicate]
I am currently struggling with the following challenge.
In the system I am currently designing, the transmitting device is equipped with an image sensor with MIPI output (1 data line, 12 Mbit data ...
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Transmitting high-speed PWM over RF
First, let me apologize in advance if this isn't the correct exchange to post this question on.
I have a 50 MHz PWM signal (it's actually a 50 MHz 50% DC clock with a 1PPS clock embedded with PWM) ...
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Clock data recovery waveform
I've read that a CDR block recovers clock from the data stream. Clock Data Recovery
Can someone show me a waveform on how its done? Like the carrier wave and modulation wave in FM and AM techniques, ...
user220456
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Modelling digital DLL for CDR for simulation/modelling purposes only
I have done a Verilog module for clock and data recovery (CDR) using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a (clock that has ...
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How do I know when I have to use clock domain crossing? [closed]
What is the reason behind clock domain crossing? When do I use it?
Do I use it only when I am transferring data from one CLK to another?
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What kind of PLL is used to recover the clock from E.G. USB 2.0 data stream
I would like to create a communication protocol to connect two FPGAs. I would like it to be fairly fast, (a couple of 100s of Mbps) but only use a single differential pair.
This kind of thing is ...
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Disadvantages of DLL clock generators compared to PLL
I've been learning from many publications that DLLs offer various advantages over PLLs, such as low-jitter performance and fast locking. So, recently, DLLs have been used for local clock generation in ...
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Bit banging synchronous serial protocol on SAME70
I am trying to implement synchronous Serial protocol with SAME70 using board SAME70-XPLD. For that I need to generate clock of 2MHz. For that I am using TC module running at MCK/8 = 18.75MHz (MCK set ...
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SyncE over wireless?
Doesn't look like "Synchronous Ethernet" exist over wireless like it does on wired. Is there any technical reason for it not existing?
On wired, Synchronous Ethernet transfers a 125 MHz master clock ...
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crystal oscillator as backup (or with sync)
I have a device that generates a 49.152MHz frequency, but depending on its status it can cut it off from time to time. This frequency synchronizes my MCU's audio devices, but it must never be stopped. ...
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Ethernet PHY clock and sync
I have a general question about reference clocks for ethernet PHYs.
The PHYs I have seen so far require an external clock source like a xtal or other singleended clock (in addition to the clk lines ...
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Could someone explain what is clock data recovery?
I have read that clock data recovery is essential for decoding signals, for instance decoding output of rotary encoders
But I don't know how it helps to decode signals.
Any hint or reference would ...
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In clock recovery, how is the recovered clock used to recover data?
I've been refreshing my memory on clock recovery, and I've hit some issues trying to understand how the recovered clock can be practically used to latch data bits from the input data stream.
For ...
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Displayport clock recovery
The displayport protocol runs at a fixed frequency of either 1.62GHz, 2.7GHz, or 5.4GHz. The pixel stream (strm_clk) it carries runs at an arbitrary frequency and is likely to be asynchronous to the ...
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Reconstructing Clock for Serial Signal
Suppose that I have a serial signal (example below), which is transmitted without an accompanying clock signal, I would like find a circuit (using discrete components / ICs, possibly an FPGA, but not ...
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