Questions tagged [clock-speed]

Anything related to clock signal frequency (a.k.a. clock speed) issues in digital systems.

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62 views

How can I create a long (10 second) pulse from a short active pulse?

So let's say I have an incoming signal: 1 clock cycle from a ~1-100 MHz (50 MHz for this example) clock domain. And I want to drive an output that must be active high for 10 seconds for each time the ...
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42 views

Clock Generation from Oscillator

Is there specific standard ways to generate clocks from oscillators? Referring to generating a square-wave clock from a sinusoidal oscillator output. I can think of a few circuits involving diodes as ...
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50 views

Sleep vs low frequency

Some processors have a low frequency mode for using in low power mode. For example MSP430 microcontroller can work in both Normal clock frequency 16M Hz Low clock frequency 32 kHz I am wondering if ...
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119 views

What is the significance of 111 in clock speed?

Never really thought about it until recently, but it looks like the number 111 appears very frequently in clock speeds and such: the first example that comes to my mind is one of the handheld game ...
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57 views

How to query APB1 clock frequency?

I'm trying to query the current value of the APB1 clock frequency to input into a USART configuration. Ideally, I could just query whatever the USART2 clock source is on an STM32F302xx, in case I ...
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65 views

Micro controller clock speed requirement for delay measurement

I am trying to measure the absolute time between two 1Hz clocks (GPS PPS events) to within 50 nanoseconds. I do not necessarily care which clock occurs first, I am only looking for the delta T between ...
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111 views

SPI clock selection

Using STM32l476 controller. Master is running at 30 MHz and slave is running 15 MHz. In SPImaster, clock should be system clock/2. In slave, clock should be system clock/4. Question: My ...
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392 views

How to use 1PPS to Synchronize ESP32 Clocks and Peripherals

I've read a few posts (example) about what the 1PPS signal is and how it can be used at a high-level, but I'm still not sure how to actually implement it on a PCB schematic to sync up with my ...
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1answer
79 views

Cascade shift registers driven by single-cycle microcontroller

I'm trying to make a unit in which 4 digits can be updated in a small amount of time from a single-cycle microcontroller (preferably all digits updated within 5uS) My circuit is setup in the ...
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4answers
94 views

Could we theoretically massively increase number of parallel computations (for some problems) by getting rid of cpu clocking?

CPU clocking involves making sure that each operation or part of an operation takes exactly a certain amount of time (the machine cycle time). One way to increase the efficiency of a cpu is by ...
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899 views

Relationship between I2C drawn energy / power consumption and data rate

Referring to just what the I2C lines draw, am I wrong thinking that the higher the clock frequency the shorter the time there will be (the same amount of) current flowing through the pullups and thus ...
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154 views

Asynchronous FIFO in clock domain crossing

Clock domain crossing issue can be solved by using asynchronus FIFO with input frequency f1 is of the source domain and f2 is of the destination frequency. If the data is sent in bursts, depth can be ...
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75 views

Have I bricked my ATMEGA3328p by setting

I was playing around with setting the "system clock prescalar" (CLKPR). I'm now in a situation where I can see that the clock is 244.9KHz, using my logic analyser and the "Clock output on PORTB0" ...
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90 views

What are the advantages of a wider bus in comparison to those of a higher clock frequency? [closed]

The aim is to increase data transfer rate. I understand each may have some drawbacks and advantages. Frankly I'm not knowledgeable enough to know of many so I'd like some input from others. I know ...
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186 views

Slow clock speed with Atmega328P AVR microcontroller on breadboard

I have a small breadboard with an Atmega328p 28 pin microcontroller with a 16 MHz crystal and two 20 pF capacitors on it (similar to this demo: https://www.arduino.cc/en/Tutorial/ArduinoToBreadboard). ...
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152 views

Overclocking an image sensor for higher FPS

What happens if I overclock an image sensor? For instance the OV7670 (datasheet) which has a rated maximum system clock input (XCLK) of 24 MHz and maximum pixel clock (PCLK) of again 24 MHz. The ...
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163 views

ATmega 32 Clock Frequency Issue

I'm currently using ATmega32 device with external clock speed of 16 MHz . the problem when i use a delay of for example 16,000 ms in the software, it actually delays only a 1000 ms in actual world. I ...
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4answers
626 views

Exotic semiconductors for fast digital ASIC

I am researching exotic semiconductors for a digital ASIC with a few million logic gates which should run as fast as possible within a $30 million budget. (Specifically, I need to do a single fully-...
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1answer
125 views

Quartz Clock Accuracy

Do the vibrations of aircraft engines (or any engine, for that matter) dilute the accuracy of a quartz clock? I haven't done any kind of research or hypothesis testing, though I believe that the ...
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1answer
101 views

LCD SPI clock frequency with STM32L0 MCU

I'm designing a PCB that includes LCD Display NHD-C12832A1Z-FSW-FBW-3V3 (datasheet) connected to the STM32L071KZU6 microcontroller (datasheet). I'm afraid that the SPI interface of the LCD will not ...
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4answers
2k views

Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external crystal?

I'm building a circuit that I'd like to run at 8 MHz to begin with, but I want to be able to try it out at 10, 12, 16, 20, and, maybe, 25 MHz. I know that many microcontrollers have the ability to ...
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5answers
4k views

Why are DIMMs not equipped with a heat sink like a CPU?

I know that a DIMM is composed of a set of chips that contain control logic managing the decode and prefetching memory operations. According to a product specification, I found that newer RAM works at ...
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4answers
265 views

Maximum Clock Frequency

As an assignment for the HDL course I'm taking, I've to design an FIR Filter. The module consists of two a small combinational circuit which can be used to reset the module, another combinational part ...
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2answers
567 views

How to set external clock value for STM32F1?

I creating a project with the microcontroller STM32F101C8t. This microcontroller has an internal clock of 36MHz. My question is how to correctly set the external clock value, ie what crystal value ...
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2k views

What is the fastest arduino to PC communication method?

I am making an application that has multiple i2c sensors controlled by an Arduino Uno. I want to get all of the raw data from the sensors and transfer them to a PC as fast as possible, on which I will ...
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403 views

Correct terminology for 'clock' that doesn't oscillate?

What would be the correct term for a clock input that isn't made to oscillate per se? In an attempt to only allow input A to have any effect on a circuit at a chosen time, one could AND it with ...
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100 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
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152 views

STM32F0x1 run SYSCLK at 1MHz with 8 MHz external crystal

I am using hardware with an 8 MHz external crystal and would like to reduce the SYSCLK frequency to 1MHz. I haven't been able to do this yet. Is it possible to achieve this with certain PLL and DIV ...
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3answers
231 views

Simplest shift register test circuit - clock

I'm looking for the simplest way to test the operation of a 74HC595 shift register without complex circuitry. Currently (on a breadboard) I have a 47K SIP resistor in a pull-up fashion connected to ...
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657 views

PLL vs Higher frequency crystal oscillator for fpga [closed]

I need 100MHz clock frequency to implement my HDL design on an FPGA. Is it better to use an FPGA board with 100MHz crystal oscillator or use PLL to increase the frequency? What are the advantages and ...
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0answers
39 views

Faster 8051 not taking the slower 8051 pin status correctly

I'm trying to do a rather simple data transaction between two 8051 microcontrollers using a variant of the SPI protocol. The large one is a slave and the small one is a master. The documentation for ...
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3answers
138 views

What determines the maximum size of a cpu cache?

Looking at a list of the very latest CPUs, I see several of them with a cache size of 12MB or 8MB - pretty small, when compared to the ever-increasing size of hard drives and ram. It seems to be taken ...
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1answer
240 views

Codec in 'master mode' require more than one external clock? (MCLK?) to drive I2S system timing to/from MCU slave?

Does an audio codec in 'master mode' require more than the one clock line (MCLK?) to drive and time I2S data sync to MCU or FPGA slave? I understand that the I2S proper consists of three lines - '...
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2answers
879 views

Why do micro controllers run @ 100's MHz whilst CPUs run @ GHz? [closed]

Whoopie - I've got a Raspberry Pi. When doing stuff it runs @ 1.2GHz and there are Uber overclockers out there who have boosted them to 1.5GHz (with phase change coolers). Today, the cheapest CPU on ...
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1answer
74 views

Is it possible to connect eight digital inputs to a digital output? [closed]

Can eight digital inputs (at 20-Mhz) output to 160-Mhz? Does a multiplexer work for this? Thanks for your answers.
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1k views

Does a baudrate in serial communication (USB or RS232) need to be exact?

In serial communication, does the baudrate mean we have to use the exact clock speed or is it a range of speeds that we can use? and if it's an exact value, how exact should it be ? for example, can ...
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1answer
524 views

How to set ADC clock in low power mode?

I am measuring the voltage with the STM32L011K4 MCU. When the processor goes into low power sleep mode, I start reading the wrong values from an ADC. I think the reason is caused by the system clock ...
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2answers
2k views

Is there an ideal PCB trace width for data lines?

For a 1oz FR-4 PCB, is there an ideal PCB trace width for data lines? For power supplies, I realize wider is usually better, and power planes are preferred. But what about data lines? Is narrower ...
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1answer
196 views

STM32F746 Clock not reporting as expected

I'm using an STM32F746VGT6 microcontroller configured from STM32CubeMX for all the clocks and I'm getting roughly 220% higher clock rates when compiled. For instance I have an HSE crystal at 11....
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5k views

HSI and MSI - Applications of two Internal RC OSC in Microcontroller

In a ST microcontroller I'm using there are two OSC's that can be routed to exactly the same hardware and I'm wondering when you would use each one. Link to part documentation STM32L496ZG Excerpt ...
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3answers
3k views

How to configure Atmel SAM D20 for internal 48MHz clock source?

I try to run a Atmel SAM D20 MCU at 48MHz using the internal oscillator (OCM8M) and the digital frequency locked loop (DFLL48M). All I achieve is a deadlock of the processor, even I use a simple "...
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2answers
1k views

RPi GPIO speed issue in bare metal

After reading the excellent article on bare metal by David Welch (https://github.com/dwelch67/raspberrypi/tree/master/baremetal), a friend and I are trying to implement a simple GPIO toggle. It's ...
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1k views

FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a ...
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3answers
7k views

How is 255 Tbit/s processed in optical fiber communication?

I have never understood how the new record breaking data transfer speeds are achieved in terms of converting from/to electrical and optical signals. Suppose we have 255 Tbits of data and we want to ...
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2answers
219 views

How to theoretically determine max clock speed for a circuit?

I was wondering what influences the max clock speed and how to calculate it for a circuit implementation. Let's take a CPU for example: From what I understand the clock speed has to be choosen so ...
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4answers
103 views

Little change in Verilog module results in high change in power consumption (Synopsys Design Compiler)

I am comparing two Verilog designs: Design (1): A top module that is driven by a clock running at 50MHz, which is the main system clock. Design (2): The same top module as in Design (1) with one ...
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4answers
2k views

Is a 4/3 clock divider possible?

I have seen designs for digital clock dividers, which can divide a clock frequency by 1.5, 2.5, etc. But is it possible to create digital logic which divides a clock by 4/3? For example, if I have a ...
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2answers
4k views

Why are there 2 clock rates (core vs memory clock) in the GPU?

I learned at school that the clock rate inside a computer is the signal that keep switching between 0 - 1 (or active - inactive). There's also another delayed clock with the same frequency. These 2 ...
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1answer
71 views

How to calculate latency of integrated product?

Is there a standard model for estimating the additional clocking latency which needs to be applied based on product interconnects? For example: Lets say a DDR memory has a switching time of 1 ns. ...
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5answers
281 views

Why is modifying (by adding extra gates) clock inputs undesirable?

I am taking a course in digital electronics at university. I am second year mechanical engineering student, but I felt like it was important to understand some electronics. The lecturer in one of the ...